Geometric-arithmetic parallel processor

Details Geometric-arithmetic parallel processor Geometric-arithmetic parallel processor

1983-03-10

1988-04-19

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1516

Patent

active

047394749

ABSTRACT:
A plurality of identical processor cells arranged interconnected to form a data processor for processing digital data signals.
Each of the cells includes an arithmetic processing element having three input terminals and two arithmetic output terminals. A plurality of memories connected to said arithmetic processing element are individually controllable to supply selected ones of a plurality of predetermined data signals to the input terminals of said processing element in response to control signals from a controller. The memories are connected to the arithmetic processing element and the controller such that both logical and arithmetic operations are performed by the arithmetic element. The data processor includes n times m cells interconnected in an m by n matrix with interior cells and edge cells.
The arithmetic processing element, preferably is a full adder having two data input terminals, a carry input terminal, a sum output terminal and a carry output terminal, and the plurality of memories includes first, second and third single-bit data registers, each selectively controllable to load one of the plurality of predetermined data signals, and a multi-bit memory such as a RAM having an output terminal and selectively addressable storage locations.

REFERENCES:
patent: 3701976 (1972-10-01), Shively
patent: 3815095 (1974-06-01), Wester
patent: 4065808 (1977-12-01), Schomberg et al.
patent: 4215401 (1980-07-01), Holsztynski et al.
patent: 4314349 (1982-02-01), Batcher
patent: 4524455 (1985-06-01), Holsztynski et al.
European Search Report with attached British Patent No. 1,536,933, Dec. 29, 1978.

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