Generic register interface for accessing registers located...

Details Generic register interface for accessing registers located... Generic register interface for accessing registers located...

1999-05-28

2004-04-13

Ho, Duc (Department: 2665)

Multiplex communications

Diagnostic testing

Of a switching system

C375S354000, C709S237000

Reexamination Certificate

active

06721277

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to data processing systems, and more particularly, to a network switch having a system for providing external CPU's access to registers run at different clock rates.
BACKGROUND ART
A network switch may be provided in a data communication network to enable data communication between multiple network nodes connected to various ports of the switch. A logical connection may be created between receive ports and transmit ports of the switch to forward received frames to appropriate destinations. The network switch may contain registers arranged in various blocks run at different clock rates, i.e. located in different clock domains.
It would be desirable to create a system for providing an external CPU with access to registers located in different clock domains. Also, it would be desirable to provide a generic register interface that supports register access by any external host connected to the network switch.
DISCLOSURE OF THE INVENTION
The invention offers a novel method of providing an external host processor with access to registers located in different clock domains. The method comprises the steps of translating host processor interface signals into internal register interface signals, and performing handshaking with the registers via the internal register interface.
The handshaking may include supplying the registers with a register access signal for enabling access to a selected register, and producing a register ready signal in response to the register access signal. Synchronization signals delayed with respect to the register ready signal may be used for synchronizing the host processor interface with the registers located in different clock domains.
In accordance with one aspect of the invention, data processing system connected to an external host processor comprises a host processor interface for providing interface to the host processor, a plurality of register modules located in different clock domains and having registers to be accessed by the host processor, an internal register interface for providing interface to the plurality of register modules, and a processor interface module coupled to the host processor interface for performing handshaking with the plurality of register modules to provide the host processor with access to the registers in the plurality of register modules. The processor interface module enables the internal register interface to support any external processor connected to the host processor interface.
In accordance with a preferred embodiment of the invention, the processor interface module may comprise a state machine responsive to the host processor interface for controlling access to the registers via the internal register interface. The state machine makes the transition to a starting state when the host processors access to a selected register is initiated. In response to initiation of the host processor's access, the state machine may produce a register access signal in the internal register interface to enable access to the selected register. A register module containing the selected register responds with a register ready signal. Thereafter, the register module may generate synchronization signals to provide synchronization with the processor interface module.
After receiving the synchronization signals, the state machine may deactivate the register access signal to finish the host processor's access. The register module may respond by deactivating the register ready signal and the synchronization signals.
In accordance with another aspect of the invention, a network switching system for switching data packets between multiple ports comprises a plurality of receive ports for receiving data packets, a decision making engine responsive to the received data packets for controlling transmission of the received data packets to a selected transmit port, a host processor interface for connecting a host processor, multiple register modules located in different clock domains, an internal register interface for providing interface to the multiple register modules, and a processor interface module coupled to the host processor interface for supporting host processor's access to registers located in different clock domains.


REFERENCES:
patent: 4590467 (1986-05-01), Lare
patent: 5515376 (1996-05-01), Murthy et al.
patent: 5867731 (1999-02-01), Williams et al.
patent: 6112298 (2000-08-01), Deao et al.
patent: 6320859 (2001-11-01), Momirov
patent: 6373841 (2002-04-01), Goh et al.

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