Generic bus system

Multiplex communications – Channel assignment techniques – Using time slots

Reexamination Certificate

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Details

C370S257000, C370S443000, C370S462000

Reexamination Certificate

active

06501766

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of multipurpose bus systems, and more particularly to a communication system where a variety of modules communicate with one another using different protocols through a shared communications bus.
BACKGROUND OF THE INVENTION
Many complex electric systems require a plurality of buses to accommodate different schemes for communications between individual modules. These schemes can be, for example, a time-division-multiplexed scheme and a data packetized scheme, where each scheme is associated with a different bus configuration. External devices together with the internal modules intercommunicate over a plurality of system buses. An example of four such buses are: a time division bus, a packet bus, a serial control bus and an address/data bus. These different buses are utilized to facilitate different types of communications.
FIG. 1
illustrates a representation of a traditional multiple bus system
10
for establishing communications between two modules
12
A and
12
B. The modules
12
A and
12
B traditionally required specific and specialized interfaces to communicate with one another. In particular, the system
10
includes a plurality of dedicated buses: a transmit datapath bus
14
, a receive datapath bus
16
, a control signal bus
18
, a status bus
20
, and a microprocessor bus
22
. These dedicated buses define paths that tend to be slow speed and idle most of the time therefore resulting in generally inefficient communication between the modules
12
.
A prior art solution for replacing a plurality of buses with a type of multipurpose bus is disclosed in U.S. Pat. No. 5,177,737 issued Jan. 5, 1993 titled Multipurpose Bus System. This patent teaches a multipurpose bus of a predetermined number of leads, as opposed to a plurality of buses individually comprising a different number of leads. In particular, the multipurpose bus includes a lead to carry a superframe signal; a lead to carry a clock signal; four leads for assignment; and a variable number of leads as the main bus. A bus manager is used to control the use of the bus in a time-sharing manner. For example, the bus manager could allocate 60% of the time to have the variable leads of the bus configured as a time division bus, 11% as a packet bus, 4% as a serial control bus and 25% as an address/data bus.
To accomplish this division of bus usage, the bus manager assigns time slices on a frame for the specific type of protocol. For example, 154 time slices can be assigned during which the bus is used as a time division bus, 30 time slices as a packet bus, eight time slices as a serial control bus and 64 time slices as an address/data bus. As a result, during the time slices when the bus is assigned to be configured as a time division bus, the modules having time division interfaces are electrically connected to the bus and modules lacking time division interfaces are disabled.
Although the multipurpose bus of the '737 patent supports the interconnection of modules having various communication protocols requiring different buses, the overhead and planning required to actually configure the bus for certain types of traffic from specific modules make it unsuitable for high speed (622 MHz-1.2 Hz) switching applications, for example.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a generic bus system where a plurality of modules can communicate with one another using different protocols through a shared communications bus.
In accordance with an aspect of the present invention there is provided a communication system wherein a plurality of modules communicate with one another using different protocols through a shared communications bus which said system comprising: means for defining a frame having a plurality of time slots for communicating signals on the bus; and means for specifying a receive assignment definition and a transmit assignment definition, said receive assignment definition defining a receive channel for each of the modules representing a set of the time slots, wherein said modules receive signals from the bus during the set of time slots prescribed by the receive channel; said transmit assignment definition defining a transmit channel for each of the modules representing a set of the time slots, wherein said modules transmit signals to the bus during the set of time slots prescribed by the transmit channel.
In accordance using another aspect of the present invention there is provided a communication system comprising: a data bus; a plurality of modules communicating over the data bus with different communication protocols; a clock bus providing a clock signal and a framing signal for defining a frame having a plurality of time slots for communicating signals on the data bus; and a bus management algorithm for specifying a receive assignment definition and a transmit assignment definition, said receive assignment definition defining a receive channel for each of the modules representing a set of the time slots, wherein said modules receive signals from the bus during the set of time slots prescribed by the receive channel; said transmit assignment definition defining a transmit channel for each of the modules representing a set of the time slots, wherein said modules transmit signals to the bus during the set of time slots prescribed by the transmit channel.
In accordance with another aspect of the present invention there is provided a method for use in a communication system wherein a plurality of modules communicate with one another using different protocol through a shared communications bus which said method comprising the steps of: defining a frame having a plurality of time slots for communicating signals on the bus; and specifying a receive assignment definition and a transmit assignment definition, said receive assignment definition defining a receive channel for each of the modules representing a set of the time slots, wherein said modules receive signals from the bus during the set of time slots prescribed by the receive channel; said transmit assignment definition defining a transmit channel for each of the modules representing a set of the time slots, wherein said modules transmit signals to the bus during the set of time slots prescribed by the transmit channel.


REFERENCES:
patent: 4750171 (1988-06-01), Kedar et al.
patent: 4809270 (1989-02-01), Baxter et al.
patent: 5046064 (1991-09-01), Suzuki et al.
patent: 5177737 (1993-01-01), Daudelin et al.
patent: 5506969 (1996-04-01), Wall et al.
patent: 5687326 (1997-11-01), Robinson
patent: 5719858 (1998-02-01), Moore
patent: 5719860 (1998-02-01), Maison et al.
patent: 5875309 (1999-02-01), Itkowsky et al.
patent: 5953344 (1999-09-01), Dail et al.
patent: 6011801 (2000-01-01), Solomon
patent: WO 96/41274 (1996-12-01), None

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