Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-06-16
2001-10-30
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C365S226000, C365S189110, C327S543000
Reexamination Certificate
active
06310511
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a generator scheme and circuitry for overcoming resistive voltage drops on power supply lines found on chips without the disadvantage of a general voltage increase such as increased current consumption and reduced reliability of the circuitry.
BACKGROUND OF THE INVENTION
Modem chips such as Dynamic Random Access Memory (DRAM) chips usually comprise several power supply systems, with each supply voltage being regulated to its nominal value. For good circuit performance (e.g., speed), it is desirable to have high voltage levels for these supply voltages for handling variable current loads. However, higher voltage levels also have undesired effects. Current consumption increases, and the potential life span of the circuit decreases. Therefore, a nominal value for each supply voltage has to be a compromise between these conflicting requirements. The generator circuits usually keep their supply voltage at their output close to the nominal value, even under load conditions. However, between the generator and the circuit that is being supplied, a significant voltage drop can occur due to the resistance of the power bus.
Referring now to
FIG. 1
, there is shown typical block diagram of a prior art exemplary chip
10
, such as a VINT generator system of a Dynamic Random Access Memory chip. The chip
10
comprises four areas
12
(shown as dashed line rectangles) adjacent each comer of the chip
10
, two horizontal buses in a “spine” section
18
and two vertical buses
14
in an “arm” section
19
which are coupled together at the center of the chip
10
, and a plurality of generators or regulators of which an exemplary eight generators
16
A-
16
H are shown. The generators
16
A-
16
H are arbitrary located along the horizontal buses
14
in the “spine” section
18
. The buses
14
in the “spine” section
18
and in the “arm” section
19
are coupled to various circuits (not shown) located in the four areas
12
and in the “spine” and “arm” sections. The arrangement of
FIG. 1
shows an exemplary DRAM chip
10
where the various circuits in the areas
12
comprise memory circuits (not shown). Due to the fact that all of the generators
16
A-
16
H are located in the “spine” section
18
, a stable supply voltage can be guaranteed in the “spine” section
18
under all load conditions. However, certain load conditions (operation modes) of the chip
10
can occur in which a large current is consumed in the “arm” section
19
. In this case a significant voltage drop occurs between the “spine” section
18
and circuits supplied in the “arm” section
19
.
Referring now to
FIG. 2
, there is graphically shown exemplary curves of voltage (volts) on the vertical axis versus time in nanoseconds on the horizontal axis, with a first curve
22
representing exemplary measurements that may be found near a central point where the “spine” and “arm” sections
18
and
19
meet near the generators
16
C-
16
F on the prior art chip
10
of
FIG. 1
, and a second curve
24
representing exemplary measurements that may be found at an end point in the “arm” section
19
of the prior art chip
10
of
FIG. 1. A
current load (not shown in
FIG. 1
) that is located at the end of the “arm” section
19
is turned on at a the time of
10
nanoseconds (ns) and turned off at 300 ns in FIG.
2
. After an initial voltage drop shown at approximately 35 ns for curve
22
, the generator regulates the voltage at its output back to almost its nominal value. At the point of the current load shown by curve
24
, the regulated voltage is seen to drop to a value of approximately 100 millivolts (mV) below the nominal value shown in curve
22
. Still further, the initial voltage drop in the curve
24
is 100 mV lower than that found at the output of the generator.
Theoretically, it is possible to size the power bus
14
into the “arm” section
19
in a way that the resistive voltage drop is kept at a minimum. However, this results in unfeasible large dimensions for the power bussing of the “arm” section
19
. Another theoretical possibility is to place generator or regulator circuits in the “arm” section
19
so that they are closer to the supplied circuits. However, due to space and floor-planning conditions on the chip
10
, this is also not feasible. A third possibility is to set the nominal voltage level higher by an amount of the maximum resistive voltage drop found in the “arm” section
19
. This, however, would conflict with reliability and current requirements on the chip
10
.
It is desirable to provide method and apparatus for a generator system on a chip for overcoming resistive voltage drops on power supply lines by rapidly reacting to increased current consumption while not reducing the reliability of a circuit coupled to the power supply lines without the disadvantages caused by a general voltage increase.
SUMMARY OF THE INVENTION
The present invention is directed to method and apparatus for a generator system on a chip for overcoming resistive voltage drops on power supply lines by rapidly reacting to increased current consumption while not reducing the reliability of a circuit coupled to the power supply lines without the disadvantages caused by a general voltage increase.
Viewed from one aspect, the present invention is directed to apparatus for controlling voltage generators of a generator system on a chip. The apparatus comprises at least one generator, a power bus, and at least one detector circuit. The at least one generator generates a predetermined amount of power to load circuits on the chip. The power bus is directed along at least one first section on the chip for supplying power from the at least one generator to the load circuits on the chip. The power bus comprises a feedback lead from each end of the power bus which is remote from the at least one generator to a predetermined point along the at least one section which is near the at least one generator for providing a continuous measurement of a voltage drop occurring at each remote end of the power bus. The at least one detector circuit is located at the predetermined point of the at least one section near the at least one generator for comparing a voltage from the at least one generator measured at the predetermined point with the voltage drop measured at a remote end of the power bus. In response to such measurements. the at least one detector circuit provides control signals to the at least one generator for altering a generated voltage to maintain a predetermined power level on the power bus in response to load changes caused by the circuits on the chip.
Viewed from another aspect, the present invention is directed to apparatus for controlling voltage generators of a generator system on a chip comprising at least one generator, a power bus, and at least one detector circuit. The at least one generator generates a predetermined amount of power to load circuits on the chip. The power bus is directed along a “spine” section on the chip which intersects with an “arm” section on the chip. The power bus supplies power from the at least one generator, which is coupled to the power bus in the “spine” section thereof, to circuits in adjacent sections of the chip. The power bus comprises a feedback lead from each end of the “arm” section to at least the intersection of the “spine” and “arm” sections for providing a continuous measurement of a voltage drop occurring at each end of the “arm” section. The at least one detector circuit is located adjacent the intersection of the “spine” and “arm” section of the chip for comparing a voltage from the at least one generator measured at the intersection of the “spine” and “arm” sections with the concurrent voltage drop measured at each remote end of the “arm” section. The at least one detector circuit provides BOOST and SPEED control signals to the at least one generator for altering a generated voltage to maintain a predetermined power level on the power bus in response to load changes caused by the circuits in the adjacent sections of the chip.
Viewed f
Braden Stanton C.
Cunningham Terry D.
Infineon - Technologies AG
Tra Quan
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