Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2011-02-22
2011-02-22
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Reexamination Certificate
active
07895551
ABSTRACT:
Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).
REFERENCES:
patent: 2008/0092090 (2008-04-01), Miyahara et al.
Barr Graham McLeod
Bittlestone Clive David
Gurumurthy Girishankar
Shah Dharin
Torvi Pavan Vithal
Brady W. James
Chiang Jack
Parihar Suchin
Pessetto John R.
Telecky , Jr. Frederick J.
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