Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1998-11-13
2001-05-08
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S538000
Reexamination Certificate
active
06229379
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a negative voltage generating circuit, which is provided on a same chip as another semiconductor circuit such as a flash memory to generate and output a negative voltage.
2. Description of the Related Art
A negative voltage is typically used to erase a content stored in a flash memory. However, a voltage supplied to the flash memory is typical a positive voltage, and the negative voltage is not supplied. Thus, a negative voltage generating circuit is provided on the same chip as the flash memory and is used to generate the negative voltage.
FIG. 1
is a block diagram showing the structure of a conventional negative voltage generating circuit. The conventional negative voltage generating circuit will be described with reference to FIG.
1
.
This conventional negative voltage generating circuit is composed of a voltage dividing circuit
82
, a comparing circuit
3
, an oscillator
4
, a clock buffer
5
, a negative voltage charge pump
6
.
The voltage dividing circuit
82
divides a voltage between a negative voltage
104
and a power supply voltage Vcc to output a divided voltage
102
. The comparing circuit
3
compares a voltage value of a reference voltage
120
with a voltage value of the divided voltage
102
. The comparing circuit
3
sets an oscillator control signal
103
to an active state when the voltage value of the divided voltage
102
is equal to or higher than that of the reference voltage
120
, and sets the oscillator control signal
103
to an inactive state when the voltage value of the divided voltage
102
is lower than that of the reference voltage
120
.
A specific structure of the comparing circuit
3
will be described with reference to FIG.
2
. Referring to
FIG. 2
, the comparing circuit
3
is composed of a resistor
97
, P-channel MOS transistors
91
and
92
of a current mirror circuit, a P-channel MOS transistor
93
whose gate receives the reference voltage
120
, a P-channel MOS transistor
94
whose gate receives the divided voltage
102
, N-channel MOS transistors
95
and
96
of a current mirror circuit and an inverter
98
.
In the P-channel MOS transistor
91
, a current determined based on the property thereof and the resistor
97
flows between a source and a drain of the transistor
91
. The current having the same current value as that flowing through the transistor
91
flows between a source and a drain of the P-channel MOS transistor
92
, which constitutes the current mirror together with the P-channel MOS transistor
91
. In this way, the P-channel MOS transistor
92
functions as a current source that supplies the current to the P-channel MOS transistors
93
and
94
. The N-channel MOS transistors
95
and
96
constituting the current mirror circuit are respectively connected to the P-channel MOS transistors
93
and
94
as the loads thereto.
When the voltage value of the divided voltage
102
is equal to or higher than that of the reference voltage
120
, the current flowing between a source and a drain of the P-channel MOS transistor
94
is decreased. When the divided voltage
102
is lower than the reference voltage
120
, the current flowing between the source and the drain of the P-channel MOS transistor
94
is increased. As a result, when the divided voltage
102
is equal to or higher than the reference voltage
120
, a voltage outputted to the inverter
98
is decreased. When the divided voltage
102
is lower than the reference voltage
120
, the voltage outputted to the inverter
98
is increased. In this way, the voltage supplied to the inverter
98
is changed in a range of a certain amplitude, in accordance with whether the divided voltage
102
is higher or lower than the reference voltage
120
. Thus, when a logical threshold of the inverter
98
is set to a value within the amplitude, the oscillator control signal
103
can be generated to indicate whether the divided voltage
102
is higher or lower than the reference voltage
120
.
The oscillator
4
generates and outputs two oscillator output signals
105
and
106
whose phases become opposite to each other, when the oscillator control signal
103
is in the active state. A specific structure of the oscillator
4
will be described with reference to FIG.
3
.
As shown in
FIG. 3
, the oscillator
4
is a ring oscillator composed of a NAND circuit
110
and inverters
111
1
to
111
6
.
The NAND circuit
110
is provided in a loop of this ring oscillator. The oscillator control signal
103
is supplied to one input terminal of the NAND circuit
110
. Thus, the oscillator control signal
103
is used to stop the operation of the oscillator
4
, when the oscillator control signal
103
is in the inactive state of a low level. The inverters
111
1
to
111
6
are connected in series in the form of a ring. An output of the inverter
111
6
is outputted as an oscillator output signal
105
, and an output of the inverter
111
5
is outputted as an oscillator output signal
106
.
FIGS. 4A
to
4
C are timing charts showing operations of the oscillator control signal
103
and the oscillator output signals
105
and
106
. Referring to
FIG. 4A
to
4
C, it could be understood that when the oscillator control signal
103
is in the active state of a high level, Vcc, the two oscillator output signals
105
and
106
whose phases are opposite to each other are outputted, and when the oscillator control signal
103
is in the inactive state of a low level, GND, the oscillator output signals
105
and
106
are not outputted.
As shown in
FIG. 5
, the clock buffer
5
receives the oscillator output signals
105
and
106
outputted from the oscillator
4
, and then outputs as complementary pulse signals
107
and
108
though inverters
121
and
122
and inverters
123
and
124
, respectively.
The negative voltage charge pump
6
generates and outputs the negative voltage
104
from the complementary pulse signals
107
and
108
. A specific structure of the negative voltage charge pump
6
will be described with reference to FIG.
6
.
As shown in
FIG. 6
, the negative voltage charge pump
6
is composed of P-channel MOS transistors
131
1
to
131
6
, capacitors
132
1
, to
132
6
and a P-channel MOS transistor
133
. The P-channel MOS transistors
131
1
, to
131
6
are connected in series such that a gate and a source of each P-channel MOS transistor are connected to each other and further a source of one transistor and a drain of another transistor are connected to each other between the transistors adjacent to each other.
The drains of the P-channel MOS transistors
131
1
,
131
3
and
131
5
are connected to the complementary pulse signal
107
through the capacitors
132
1
,
132
3
and
132
5
, respectively. Also, the drains of the P-channel MOS transistors
131
2
,
131
4
and
131
6
are connected to the complementary pulse signal
108
through the capacitors
132
2
,
132
4
and
132
6
, respectively. The source of the P-channel MOS transistor
131
1
is outputted as the negative voltage
104
, and the drain of the P-channel MOS transistor
131
6
is connected to the source of the P-channel MOS transistor
133
. The gate and drain of the P-channel MOS transistor
133
are connected to the ground to set the drain of the P-channel MOS transistor
131
6
to a ground potential.
An operation of the negative voltage charge pump
6
will be described below. For the purpose of simple explanation, the operation will be described by using only the P-channel MOS transistor
131
2
. However, the operations of the other P-channel MOS transistors
131
1
,
131
3
to
131
6
are similar to those of the P-channel MOS transistor
131
2
. For the purpose of explanation, the source of the P-channel MOS transistor
131
2
is assumed to be a node
13
a
, and the drain thereof is assumed to be a node
13
b.
At first, it is assumed that at a certain timing, the complementary pulse signal
107
is set to the power supply voltage Vcc and the complementary pulse signal
108
is set to the
Callahan Timothy P.
Foley & Lardner
NEC Corporation
Nguyen Hai L.
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