Generation of multiple simultaneous random test cycles for hardw

Details Generation of multiple simultaneous random test cycles for hardw Generation of multiple simultaneous random test cycles for hardw

1998-06-01

2000-08-29

Teska, Kevin J.

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Software program

703 14, 703 15, 703 16, G06F 1750

Patent

active

061102180

ABSTRACT:
Multiple test cycles may be randomly generated for simultaneous execution on a design under test using a simultaneous random cycles test generator. One form of the test generator is hardware description code run on a simulator. The test generator provides multiple random cycle description generators. A random cycle description generator randomly generates a particular test cycle at runtime using constraints provided by the test generator. A random cycle description generator granted access to a serial common cycle initiator may initiate random test cycles through the common cycle initiator. The common cycle initiator may execute the randomly determined test cycle or define and arm a cycle executor of a plurality of cycle executors to execute the randomly determined test cycle. While one random test cycle is executed, another random cycle description generator is selected to initiate another random test cycle on the common cycle initiator. The newly initiated test cycle is then executed while the initial test cycle is executing, accomplishing simultaneous execution of multiple test cycles. The delay following generation of one random test cycle before generation of another random test cycle is randomly determined. Attributes for a test cycle are also randomly determined. A simultaneous random cycles test generator provides verification of design-specific functions of a design under test which may be randomly and simultaneously changed.

REFERENCES:
patent: 5594741 (1997-01-01), Kinzelman et al.
Nachman et al.; "Random pattern testing for sequential circuits revisited"; IEEE--Proc. Symp. Fault Tolerant Computing; pp. 44-52, Jun. 1996.
Hortensius et al; "Parallel random number generation for VLSI systems using cellular automata"; IEEE--Trans. Computers; pp. 1466-1473, Oct. 1989.

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