Pulse or digital communications – Receivers – Particular pulse demodulator or detector
Reexamination Certificate
1999-09-20
2003-07-01
Bocure, Tesfaldet (Department: 2631)
Pulse or digital communications
Receivers
Particular pulse demodulator or detector
C375S290000
Reexamination Certificate
active
06587520
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to the field of digital signal reception and more specifically, to the field of maximum likelihood bit detection in which signal amplitudes in a digital signal are used to determine the most likely bit signal.
The invention relates to an apparatus for deriving amplitude values from an input information signal, which amplitude values can be used as reference levels for the states of a finite state machine, which are needed for the computation of the likelihood functional in a partial response maximum likelihood (PRML) bit detection apparatus. The PRML bit detection apparatus is based on a finite state machine with states corresponding to specific bit sequences.
PRML detection requires reference amplitude-levels for each state in the corresponding finite-state-machine (FSM), from which the likelihood of different paths is computed, given the measured signal waveform. The well-known Viterbi-algorithm enables very efficient computation of the most likely path. Each state of an n-taps partial response (PR) corresponds with one of the possible n-bits environments as shown e.g. in
FIGS. 3 and 4
. In standard PRML detection, an equaliser setting is chosen so that a simple symmetrical partial response is realised in the nominal situation of zero tilt of the disc with respect to the laser beam, i.e. with simple integer-valued coefficients.
Those skilled in the art are directed to Van Den Eden, International Patent Application (PCT) filed under nr. IB97/01532, 1997; and WO/ 97/29485.
The above citations are hereby incorporated in whole by reference.
SUMMARY OF THE INVENTION
A single equaliser may not be optimal in terms of timing recovery. In such case a solution with two equalisers can be implemented, with one equaliser for the timing recovery, and a second one to equalise to the partial response levels. The second one may be made adaptive so that channel fluctuations may be followed, if a robust control mechanism can be set-up, e.g. one that measures the obliqueness of the channel, e.g. from the eye-pattern, and transforms this into an adaptation of the tap-values of the equaliser. Non-linearities such as a systematic asymmetry between marks and non-marks are also a problem to be dealt with and are not accounted for in standard PRML using a linear partial response.
In accordance with the invention, the apparatus for deriving amplitude values from an input information signal, which amplitude values can be used in a partial response maximum likelihood bit detection apparatus, comprises
input means (
1
) for receiving the input information signal,
conversion means (
2
′,
6
) for deriving a digital signal from said input information signal, said digital signal comprising an array of bits of a first or a second binary value occurring at bit instants with a specified bit frequency,
detection means (
8
) for repeatedly detecting a state from subsequent sequences of n subsequent bits in said digital signal, said subsequent sequences being obtained by shifting a time window of n subsequent bits each time over one bit in time,
sample value determining means (
2
) for deriving sample values from said input information signal, one sample value for each of said sequences of n bits, said one sample value for a sequence of n bits corresponding to the signal value of said input information signal at a predetermined time instant lying within a time window corresponding to said sequence of n bits,
processing means (
4
,
12
) for processing the sample values belonging to sequences of n bits of the same state, and for carrying out this processing step for all states, so as to obtain a processed signal value for each state,
output means (
20
) for supplying the processed signal values for each state as the amplitude values that can be used in the partial response maximum likelihood bit detection apparatus.
The invention is based on the following recognition. With the apparatus in accordance with the invention accommodated in a PRML bit detection apparatus, in fact, a 2-stage process has been realised. In a first stage, a relatively simple bit detector, such as a simple threshold detector (TD), or a threshold detector that corrects for runlength constraint violations—also called: full-response maximum likelihood (FRML) detector, also known as runlength pushback detector, is used to derive bit decisions for a limited range of bits, which are further treated as a training sequence. The data of the training sequence is not a priori known, but is supposed to be well approximated by the result of TD or FRML. An implementation with a digital phase locked loop (PLL) and equaliser will be assumed. Thus, from the asynchronously oversampled signal waveform the bit-synchronously resampled waveform (BSW) for a bit-window of N samples is derived. The latter represents a walk through the finite-state machine (FSM) with step-size equal to the bit-tap, and the actual states that are visited are derived from the bit-environments obtained from TD or FRML. For each state, the measured waveforms corresponding to that state are averaged, yielding the amplitude reference level to be used in the PRML detector, which is the second stage. The walk through the FSM is error free in the case of the FRML bit decisions, but may be subject to some errors when the TD is used for deriving the training sequence.
Those skilled in the art will understand the invention and additional objects and advantages of the invention by studying the description of preferred embodiments below with reference to the following drawings which illustrate the features of the appended claims:
REFERENCES:
patent: 5113400 (1992-05-01), Gould et al.
patent: 5588011 (1996-12-01), Riggle
patent: 5666370 (1997-09-01), Ganesan et al.
patent: 5764608 (1998-06-01), Satomura
patent: 5774470 (1998-06-01), Nishiya et al.
patent: 6092230 (2000-07-01), Wood et al.
patent: 6278748 (2001-08-01), Fu et al.
patent: 6288992 (2001-09-01), Okumura et al.
US 5 588 011 a (C.m. Riggle) Dec. 24, 1996 Dec. 24, 1996 column 1, line 14 -column 15, line 9; B.H. Marcus, P.H. Siegel and J.K. Wolf: “Finite -State Modulation Codes for Data Storage” IEEE Journal On Selected Areas In Communication, vol. 10, No. 1, 1992, pp. 5-37, XP 000462064 New York p. 5, column 1, line 1-p. 37, column 2, last line.
Coene Willem M. J.
Van Der Vleuten Renatus J.
Belk Michael E.
Bocure Tesfaldet
Koninklijke Philips Electronics , N.V.
Kumar Pankaj
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