Generation of a low jitter clock signal

Details Generation of a low jitter clock signal Generation of a low jitter clock signal

2010-02-26

2011-12-27

Luu, An (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S112000

Reexamination Certificate

active

08085080

ABSTRACT:
Systems and methods for generation of a low jitter clock signal for wireless circuits are disclosed. In an implementation, the system includes a wireless circuit powered by a first power supply and a low jitter clock (LJC) generator powered by a second power supply. The LJC generator provides at least one clock signal to the wireless circuit. The system further includes an LJC driver circuit including a clock buffer powered by the first power supply and a receive buffer powered by the second power supply.

REFERENCES:
patent: 6717445 (2004-04-01), Nair
patent: 7193441 (2007-03-01), Chen et al.

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