Generation of a loose planarization mask having relaxed boundary

Details Generation of a loose planarization mask having relaxed boundary Generation of a loose planarization mask having relaxed boundary

1997-03-04

1999-07-20

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438435, 438691, 438692, 438791, H01L 2176

Patent

active

059267232

ABSTRACT:
A method of forming an improved planarization mask for shallow trench isolation process area in integrated circuit manufacturing is disclosed. The planarization mask is generated automatically by using actual mask data as a reference. The invention discloses an algorithm which measures the geometric and relative separation distances of the active areas and performs the necessary merging, deletion and differential biasing to produce the planarization mask which has relaxed geometric boundaries, thereby allowing low cost and simplified manufacturing.

REFERENCES:
patent: 4954459 (1990-09-01), Avanzino et al.
patent: 5691215 (1997-11-01), Dai et al.
patent: 5789286 (1998-08-01), Subbanna
patent: 5804492 (1998-09-01), Shen
patent: 5811345 (1998-09-01), Yu et al.

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