Generation of a clock frequency in a smart card interface

Details Generation of a clock frequency in a smart card interface Generation of a clock frequency in a smart card interface

1994-08-11

1996-01-23

Chin, Stephen

Pulse or digital communications

Repeaters

Including pulse regeneration or conversion

375220, 375376, 375377, 327147, 327156, 327160, 331 25, H04L 700

Patent

active

054870844

ABSTRACT:
A circuit arrangement for generating the clock signal of a predetermined frequency f(UART) for a smart card interface, the interface being used for transferring data from a smart card to a device e.g. a mobile telephone at a predetermined data rate f(D). Using a phase-locked loop (PLL) and a number of programmable counters (N1-N4), the output of the circuit i.e. the smart card interface clock signal can have a frequency f(UART) which is a multiple of the data rate. In particular, the counters (N1-N4) and phase-locked loop (PLL) can be chosen so that f(UART) is sixteen times f(D) which allows a Universal Asynchronous Receiver Transmitter circuit to be used in the interface.

REFERENCES:
patent: 4215245 (1980-07-01), Bellisio
patent: 4445193 (1984-04-01), Mueller et al.
patent: 4761800 (1988-08-01), Lese et al.
patent: 4815099 (1989-03-01), Shimatani et al.
patent: 5140284 (1992-08-01), Petersson et al.
patent: 5187722 (1993-02-01), Petty
patent: 5258877 (1993-11-01), Leake et al.
"Gear-Shifted Phase-Locked Oscillator"-IBM Technical Disclosure Bulletin (vol. 14, No. 9, Feb. 1972)-D. J. Malone.
IBM Technical Disclosure Bulletin vol. 30, No. 1, Jun. 1987 New York US, pp. 26-27.

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