Generation and storage of column offsets for a column...

Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit

Reexamination Certificate

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C348S302000, C348S304000, C250S2140RC

Reexamination Certificate

active

07368696

ABSTRACT:
The plural signal chains of an imaging device are calibrated in the digital domain. The pixel array of the imaging device includes a row of calibration pixels. The column circuitry, prior to reading a row of pixels, reads the row of calibration pixels in order to obtain a set of column offsets. The row of pixels is read and processed to produce a corresponding plurality of digital values. The set of column offsets are applied to the digital values to compensate for response differences among the signal chains.

REFERENCES:
patent: 6433822 (2002-08-01), Clark et al.
patent: 6473124 (2002-10-01), Panicacci et al.
patent: 6538695 (2003-03-01), Xiao et al.
patent: 7154548 (2006-12-01), Liu
patent: 2005/0094005 (2005-05-01), Xu
Takayanagi I., et al. “A 1 1/4 inch 8.3M Pixel Digital output CMOS APS for UDTV Application” IEEE Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International San Francisco, CA, USA US, Feb. 9, 2003, pp. 1-8.
I. Takayanagi, et al., ISSCC 2003 / Session 12 / CMOS Imagers, Sensors and Displays / Paper 12.3, 2003 IEEE International Solid State Circuits Conference.

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