Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1998-11-13
2001-05-01
Mai, Tan V. (Department: 2121)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C341S061000
Reexamination Certificate
active
06226661
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to digital signal processing, and more particularly to generation and application of sample rate conversion ratios using distributed jitter.
Digital signal processing (DSP) is widely used to perform a variety of functions, such as filtering, compression, enhancement, and others. Generally, an analog signal is preprocessed and sampled at a particular sampling frequency using an analog-to-digital converter (ADC). The sampled data can be subsequently processed using various DSP techniques known in the art.
Sample rate conversion generally refers to the process of converting samples at one rate to samples at a second rate. A sample rate conversion ratio refers to the ratio of the input sample rate to the output sample rate. Sample rate conversion may be necessitated, for example, by the need to support multiple industry standards. As an example, for digital audio, many sources are sampled at a sample rate of either 48.0 KHz or 44.1 KHz. It may subsequently be necessary to process data that has been sampled at one rate (e.g., 48.0 KHz) to generate resampled data at a second rate (e.g., 44.1 KHz). For this example, the sample rate conversion ratio is 48.0/44.1, or 160/147 (which is the lowest common denominator for 48,000/44,100).
Often times, for ease of processing, it is desirable to represent the sample rate conversion ratio as a “fractional binary ratio” having a denominator that is a power of two (e.g., 16,384 or 2
14
). However, as illustrated by the example above, the sample rate conversion ratios for some applications cannot be exactly represented with fractional binary ratios. When this occurs, one conventional technique simply approximates the sample rate conversion ratio with a nearly equivalent fractional binary ratio, and ignores the resulting error. For the example described above, a fractional binary value of 17832/16384 can be used to approximate 160/147, with a resulting error of 136/(16384·160). However, this technique is inadequate for applications that require precise sample rate conversion ratios.
SUMMARY OF THE INVENTION
The invention provides methods and circuits for the generation and application of sample rate conversion ratios using distributed jitter. In some applications, it is not possible to represent the required sample rate conversion ratio with an exact fractional binary ratio having a denominator that is a power of two. When this occurs, a fractional binary ratio is selected that closely approximates the required conversion ratio. The residual phase error resulting from the use of the selected fractional binary ratio is compensated for by adding a predetermined amount of “jitter.” The jitter can be distributed periodically, uniformly, or randomly over each repetition period (i.e., the period in which the input and output clock “pattern” repeats).
A specific embodiment of the invention provides a method for generating a sample rate conversion ratio. Initially, a least common denominator ratio for an input sample rate and an output sample rate is determined. A fractional binary ratio having a denominator that is a power of two is then selected. A residual phase error resulting from using the selected fractional binary ratio is computed. The magnitude and distribution of a phase correction jitter that accounts for the residual phase error is then determined.
Another specific embodiment of the invention provides a method for generating phases for a sample rate converter. Initially, a fractional binary ratio is selected that has a denominator that is a power of two. The fractional binary ratio represents an approximation of a required sample rate conversion ratio. Next, a residual phase error resulting from the use of the selected fractional binary ratio is computed. A base increment value is then determined in accordance with the selected fractional binary ratio, and a fractional increment value corresponding to the residual phase error is also determined. The base increment value is used to update a phase accumulator for each cycle of an output clock. A jitter corresponding to the fractional increment value is added to the phase accumulator for selected cycles of the output clock.
Yet another specific embodiment of the invention provides a method for performing a sample rate conversion. Initially, a base increment value is determined in accordance with a fractional binary ratio that approximates a required sample rate conversion ratio. Next, a fractional increment value is determined based on a computed residual phase error. For each output clock cycle, a phase value is generated in accordance with the base and fractional increment values. Sampled data are then interpolated, in part, in accordance with the generated phase value. Selected ones of the interpolated samples are provided as the output data.
The invention also provides circuits that implements the specific embodiments described above and other embodiments of the invention as described below.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.
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Julius O. Smith et al., “A Flexible Sampling-Rate Conversion Method,” IEEE International Conference on Acoustics, Speech, and Signal Processing, Mar. 1984, cover plus pp. 19.4.1-19.4.4.
Creative Technology Ltd.
Mai Tan V.
Townsend and Townsend / and Crew LLP
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