Generating non-planar topology on the surface of planar and near

Details Generating non-planar topology on the surface of planar and near Generating non-planar topology on the surface of planar and near

1998-07-06

2000-09-05

Niebling, John F.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

438633, 438692, 438693, H01L 2176

Patent

active

061142158

ABSTRACT:
A process for modifying an alignment mark is described. The process includes: (i) fabricating the alignment mark on an integrated circuit substrate surface, which alignment mark includes an alignment mark fill material of defined composition; and (ii) introducing a step in the alignment mark by polishing the integrated circuit substrate surface and removing at least some of the alignment mark fill material from the integrated circuit substrate to form a modified alignment mark. The modified alignment mark is capable of allowing an alignment tool to detect the modified alignment mark when the modified alignment mark is covered by an opaque layer and thereby align a first layer of the integrated circuit substrate to the opaque layer that is disposed above the first layer.

REFERENCES:
patent: 5846398 (1998-12-01), Carpio
patent: 5863825 (1999-01-01), Pasch et al.
patent: 5972793 (1999-10-01), Tseng

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