Generating multiple clock phases

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

08058914

ABSTRACT:
In one embodiment, a circuit includes a first circuit input for receiving a first reference signal having a first phase; a second circuit input for receiving a second reference signal having a second phase; a third circuit input for receiving a target phase signal; a circuit output for outputting an output signal; a first multiplying mixer cell (MMC) comprising a first MMC input, a second MMC input, and a first MMC output; a second MMC comprising a third MMC input, a fourth MMC input, and a second MMC output. In an example embodiment, the first circuit input is connected to the first MMC input; the second circuit input is connected to the third MMC input; the third circuit input is connected to the second MMC input and the fourth MMC input; the first MMC output and the second MMC output are combined with each other to provide the circuit output; and the output signal, when present, represents an error signal that is proportional to a phase difference between a phase of the target phase signal and an average of the first and second phases.

REFERENCES:
patent: 5039889 (1991-08-01), Janta
patent: 5343097 (1994-08-01), Takeuchi
patent: 6381291 (2002-04-01), Yom
patent: 7286625 (2007-10-01), Lee et al.
patent: 7420870 (2008-09-01), Park et al.
patent: 7444085 (2008-10-01), Ikeuchi
patent: 7535271 (2009-05-01), Kizer
patent: 2009/0149149 (2009-06-01), Rujis
patent: 2009/0237128 (2009-09-01), Qiao
patent: 2010/0085086 (2010-04-01), Nedovic
patent: 2010/0086075 (2010-04-01), Parikh
patent: 2010/0090723 (2010-04-01), Nedovic et al.
patent: 2010/0091925 (2010-04-01), Nedovic
patent: 2010/0091927 (2010-04-01), Walker et al.
patent: 2010/0104057 (2010-04-01), Nedovic
patent: 2010/0241918 (2010-09-01), Nedovic
patent: 2008/018034 (2008-02-01), None
SerDes Framer Interface Level 5 Phase 2 (SFI-5.2): Implementation Agreement for 40Gb/s Interface for Physical Layer Devices, IA# OIF-SFI5-02.0, Oct. 2, 2006.
Hanumolu, P. K. et al., “A Wide-Tracking Range Clock and Data Recovery Circuit”,IEEE JSSC,43:2, Feb. 2008.
Lee, J. et al., “A 40-Gb/s Clock and Data Recovery Circuit in O.18-/-tm CMOS Technology”, IEEE Journal of Solid-State Circuits, 38:12, Dec. 2003.
Nedovic, N. et al., “A 40-44Gb/s 3x Oversampling CMOS CDR/1: 16 DEMUX”, ISSCC Digest of Technical Papers, 2007.
Staszewski, R. B. et al, “All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS”,IEEE JSSC,39:12, Dec. 2004.
Office Action for U.S. Appl. No. 12/510,211, Aug. 23, 2010.
Office Action for U.S. Appl. No. 12/511,340, Sep. 28, 2010.
Dally, William et al., “Digital Systems Engineering,” Cambridge University Press, Cambridge, UK, 2008.
Office Action for U.S. Appl. No. 12/510,211, Feb. 10, 2011.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Generating multiple clock phases does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Generating multiple clock phases, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Generating multiple clock phases will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4268775

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.