Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2000-04-07
2004-08-17
Tran, Henry N. (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S010000, C345S087000, C348S464000, C348S521000, C348S538000
Reexamination Certificate
active
06778170
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to display units, and more specifically to a method and apparatus for generating high quality images in a display unit without being affected by error conditions in synchronization signals containing the display signals based on which the images are generated.
2. Related Art
Display units are often used to receive and display image frames contained in a display signal received on a serial communication channel. As used in the present application, display units include both analog display units (typically based on cathode ray tube technology) and digital display units (typically based on flat panels). As is well known, the image frames are represented by pixel data elements encoded within display data portion of the display signal.
Display signals generally also contain synchronization signals which indicate the demarcation of the line boundaries and frame boundaries in the accompanying display data. Examples of such signals include HSYNC (indicating transition to next line) and VSYNC (indicating transition one frame to the another) as is well known in the relevant arts.
Synchronization signals are often used to determine the specific pixel data elements which represent the image frame. That is, among the many pixel data elements contained in the display data, some correspond to the image frame and others correspond to the non-display period also. In many known display units, signals termed as VDISP and HDISP are generated (based on the synchronization signals) which respectively indicate whether an active horizontal line and active pixel data element are presently being received. The active pixels in the active lines represent image to be displayed.
One problem with the use of synchronization signals in generating signals such as VDISP and HDISP is that it may not lead to an accurate and consistent indication of the active pixel data elements (more specifically, the time position of the active pixels). The problem may be due to, for example, the fact that the synchronization signals and the display data are often generated by integrated circuits without appropriate coordination.
The result of such problems is that artifacts are introduced into the displayed images, thereby affecting the image quality. The poor image quality may not be acceptable in some situations. Therefore, what is needed is a method and apparatus which enables the images encoded in the display signals to be displayed without being affected by the status of the synchronization signals.
SUMMARY OF THE INVENTION
The present invention uses a display enable (DE) signal received in a display signal to determine the active pixel data elements representing image frames. The DE signal is generally in one logical state when an active pixel data element is encoded in a display data portion and in another logical state during the non-display period. As the DE signal may be generally expected to track (in time domain) the pixel data elements encoded in the display signal, the active pixel data elements may be accurately identified.
According to an aspect of the present invention, the DE signal is used to first generate alternative synchronization signals which are similar in characteristics to the synchronization signals present in display signals. That is, the alternative display signals (de_hsync and de_vsync) also indicate the transitions across horizontal lines and frames similar to the synchronization signals present in display signals.
The alternative synchronization signals are then used to generate VDISP and HDISP signals, which respectively indicate the time duration in which an active line and pixel data element are being received. Based on the VDISP and HDISP signals, the active pixel data elements (which represent images) are identified from among all the pixel data elements generated from the display data.
According to another aspect of the present invention, a multiplexor is used to select either the alternative synchronization signals or the synchronization received in display signals. The selected signals are used to generate the HDISP and VDISP. That is, if desired, the HDISP and VDISP may be generated based on the synchronization signals received in the display signal also.
Thus, the present invention is suited for use in analog or digital display units which receive displays signals compatible with standards such as Digital Visual Interface (DVI) or Digital Flat Panel (DFP) interface as such standards contain the DE signal used by the present invention.
The present invention enables images of superior quality to be generated as the active pixel data elements can be identified accurately.
The present invention enables a display unit to generate HDISP and VDISP signals based either on DE signal or on HSYNC/VSYNC signals as a multiplexor is provider to select either the HSYNC/VSYNC signals or the alternative synchronization signals generated based on the DE signal.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
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Digital Visual Interface DVI by Digital Display Working Group, Apr. 2, 1999 (pp. 1-53).
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Kobayashi Osamu
Shu Hongjun
Wang Wen-jyh
Beyer Weaver & Thomas LLP
Genesis Microchip Inc.
Tran Henry N.
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