Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2006-09-19
2006-09-19
Nguyen, Linh My (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S149000
Reexamination Certificate
active
07109767
ABSTRACT:
A digital delay-locked loop has been discovered having a reduced area as compared to typical register-controlled delay-locked loops (RDLLs) used to control strobe delay lines that provide delay to strobe signals driving asynchronous FIFOs. This result is achieved by reducing ratio computation (i.e. gear logic) circuitry of the RDLL. A master delay line receives a control code to delay a reference clock by one clock period. A slave delay line receives the control code to delay a strobe signal by a predetermined fraction of the clock period. The master delay line may include individual sections responsive to the control code which effectively delay a signal by a portion of the clock period, the delay having a fixed relationship to a delay associated with individual sections of the slave delay line.
REFERENCES:
patent: 6181168 (2001-01-01), Zarubinsky et al.
patent: 6289068 (2001-09-01), Hassoun et al.
patent: 6483871 (2002-11-01), Dawe
Satoshi Eto, et al., “A 1Gb SDRAM with Ground Level Precharged Bitline and Non-Boosted 2.1V Word Line,” IEEE International Solid-State Circuits Conference, 1998, pp. 82-83.
Atsushi Hatakeyama, et al., “A 256-Mb SDRAM Using a Register-Controlled Digital DLL,” IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1728-1734.
Georgios Konstadinidis, et al., “Implementation of a Third-Generation 1.1GHz 64b Microprocessor,” ISSCC 2002, Feb. 6, 2002, 3 pages.
Feng Lin, et al., “A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM,” IEEE Journal of Solid-State Circuits, vol. 34, No. 4, Apr. 1999, pp. 565-568.
Kevin Ryan, “DDR SDRAM Functionality and Controller Read Data Capture,” DesignLine, vol. 8, Issue 3, 3rdQuarter 1999, pp. 1-24.
Amick Brian W.
Gauthier Claude R.
Ramachandran Aparna
Singh Gajendra P.
Tran Tri K.
Nguyen Linh My
Sun Microsystems Inc.
Zagorin O'Brien Graham LLP
LandOfFree
Generating different delay ratios for a strobe delay does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Generating different delay ratios for a strobe delay, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Generating different delay ratios for a strobe delay will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3596957