Multiplex communications – Communication over free space – Having a plurality of contiguous regions served by...
Reexamination Certificate
1999-03-16
2003-05-06
Vo, Nguyen T. (Department: 2682)
Multiplex communications
Communication over free space
Having a plurality of contiguous regions served by...
C370S342000
Reexamination Certificate
active
06560212
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to telecommunication systems, and, more particularly, to generating offset sequences for a code-division, multiple-access (CDMA) based communication schemes.
2. Description of the Related Art
Several code-division, multiple-access (CDMA) standards have been proposed, and one such standard is the IS-95 standard adopted for cellular telephony. As with many CDMA systems, IS-95 employs both a pilot channel for a base station and data, or message, channels for communication between the base station and users. Each of the base station and users communicating with the base station employ one or more assigned, pseudo-random sequences, also known as pseudo-noise (PN) sequences, for spread-spectrum “spreading” of the channels. The PN sequences are used to spread, in frequency, data transmitted by the transceiver and to despread data received by the transceiver. The PN code sequence is used for both In-phase (I) and Quadrature-phase (Q) channels, is a sequence with a known number of bits, and is transmitted at a predetermined clock rate.
To determine when a signal is transmitted, and to synchronize reception and processing of a transmitted signal, the IS-95 standard specifies one or more correlation fingers, with each finger correlating a known portion of the PN code sequence with the sampled received signal. The pilot epoch is the time interval over which a PN sequence of a pilot signal repeats. The beginning of the PN sequence of the pilot channel occurs after the rollover state, which is the state at which the I-phase sequence and Q-phase sequence in respective PN generators have the same logic value in all register stages. The IS-95 system may insert an extra value in the PN sequence so that the length of the PN code sequence is an integer multiple of 2. The resulting augmented PN sequence is known in the art as a deBruijn sequence.
A (binary) PN sequence is a special form of linear shift register (LSR) sequence, so named since the sequences are generated with linear feedback of a shift register. Two popular LSR generators are Fibonacci and Galois code generators. Given a desired offset of K bits, the K-offset sequence may be generated with an LSR generator by either (i) re-initializing the state of the LSR or (ii) employing an appropriate linear combination of the state variables of the LSR. The offset K is an integer value, 1≦K≦2
r
−1, where r is defined as the order of the LSR PN sequence, and is generally the length of the shift register of the LSR.
The nth binary value P
n
of a PN sequence generated by an LSR generator may be defined by the following recursive formula of equation (1):
p
n
=
∑
i
=
1
r
g
i
p
n
-
i
,
(
1
)
where the g
i
are generating coefficients. Addition and multiplication of equation (1) are over the (binary) Galois field (GF(2)).
The generating function of the PN sequence P(D) is defined as given in equation (2):
P
(
D
)
=
∑
n
=
0
∞
p
n
D
n
.
(
2
)
where the value D is defined as a unit delay operator. Combining equation (1) and equation (2) provides equation (3):
P
(
D
)
=
I
(
D
)
G
(
D
)
,
(
3
)
where I(D) is the initial polynomial of the LSR sequence, the degree of which is at most r−1, and is defined as in equation (4):
I
(
D
)
=
∑
i
=
0
r
-
1
(
∑
j
=
i
+
1
r
g
j
p
i
-
j
)
D
i
(
4
)
G(D) is referred to as the generating polynomial of the LSR sequence, and is defined as in equation (5):
G
(
D
)
=
1
+
∑
i
=
1
r
g
i
D
i
(
5
)
Equation (4) and equation (5) show that the generating function P(D) of an LSR sequence is completely specified by its initial polynomial I(D) and the generating polynomial G(D), the generating polynomial G(D) being represented by the generating coefficients g
i
.
The PN sequence is periodic, with a period (number of sequence values) being the smallest integer N such that G(D) divides (1+D
N
) without a remainder. The zero-offset PN sequence having generating P
0
(D) may be defined as p
0
, p
1
, . . . , p
N−1
, p
0
, p
1
, . . . , and P
0
(D)=I
0
(D)|G(D), with I
0
(D)=I(D) of equation (4).
The PN sequence offset by K bits may be a sequence as illustrated below:
p
N
-
K
,
p
N
-
K
+
1
,
⋯
⏞
K
,
p
N
-
1
,
p
0
,
p
1
,
⋯
,
p
N
-
K
-
1
⏟
N
,
p
N
-
K
,
⋯
For a sequence offset by K bits, the “beginning” of the sequence is delayed by K bits values with respect to a reference sequence. The beginning, or zero-offset, of a periodic sequence may be arbitrarily defined within a PN sequence. For communication systems in accordance with an IS-95 standard, the reference (zero-offset) sequence is defined so that the short PN sequence starts a new cycle if the last 15 bits of the sequence from the LSR are 100000000000000 (the rollover state). For a particular implementation, additional logic may be required to insert the extra value into each sequence following 14 consecutive 1's or 0's. The extra value renders a 2
15
chip period PN sequence. Consequently, for systems such as IS-95, at the beginning of the PN sequence the value in the first register stage is forced to a logic “0” prior to the next state transition.
The generating function P
K
(D) of the PN sequence offset by K may be defined as in equation (6):
P
K
(
D
)
=
D
K
P
0
(
D
)
+
∑
i
=
0
K
-
1
p
N
-
K
+
i
D
i
=
D
K
I
0
(
D
)
G
(
D
)
+
∑
i
=
0
K
-
1
p
N
-
K
+
i
D
i
.
(
6
)
P
K
(D) may also be defined as in equation (7):
P
K
(
D
)
=
I
K
(
D
)
G
(
D
)
,
(
7
)
From equation (6) and equation (7), I
K
(D) may be defined as in equation (8):
I
K
(D)=
D
K
I
0
(
D
)mod
G
(
D
) (8)
where mod (·) indicates the “modulo value of.” Equation (8) shows the relation between the initial polynomials of the zero-offset and K-offset PN sequences. If I
0
(D) is the initial polynomial of an LSR sequence with an arbitrary offset, then I
K
(D) is the initial polynomial of the counterpart sequence with an offset of K bits. Therefore, the expression for I
0
(D) in equation (4) may given in equation (9):
I
0
(
D
)
=
∑
i
=
0
r
-
1
(
∑
j
=
i
+
1
r
g
j
p
n
+
i
-
j
)
D
i
(
9
)
for some integer n.
A maximal length PN sequence with an offset of K bits from an original maximal length PN sequence is generated with a linear combination of the state variables of the LSR that relate I
0
(D) to I
K
(D). The process of employing a linear combination of the state variables is called masking. Masking is a form of 1-to-1 mapping from the LSR state at one instant to another LSR state at the same instant.
This mapping operation with masks (or masking operation) is shown in
FIG. 1
for a maximal length PN sequence of 7 (2
r
−1). Such PN sequence of
FIG. 1
may be produced with an LSR of length 3 to yield the sequence length of 7. Each state P
i
has a corresponding set of values p
i−r
+1, . . . , p
i
, corresponding to the stages of the LSR generator shift register. For convenience, the following defines the current value of the reference PN sequence as the currently generated value p
i
. However, as would be apparent to one skilled in the art, some variations in the correspondence of the current value of the PN sequence and the value of the LSR stage may occur, depending upon whether the LSR generator is a Fibonacci or a Galois code generator. In addition, some variations may occur in the correspondence of the current value depending upon whether the sequence is provided from the last stage of the LSR or from the input to the first stage of the LSR.
As shown in
FIG. 1
, each masking operation M
ij
of a current state P
i
of the zero-offset PN sequence provides the corresponding offset value p
j
of the offset sequence. As is known in th
Prasad Mohit K.
Wang Xiao-An
Agere Systems Inc.
Hughes Ian M.
Mendelsohn Steve
Vo Nguyen T.
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