Generating an error signal when accessing an invalid memory page

Details Generating an error signal when accessing an invalid memory page Generating an error signal when accessing an invalid memory page

1997-09-09

1999-11-23

Kim, Matthew M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Interface

345503, 345520, 345514, 345522, 345526, 345515, 345507, 345509, 395306, 395309, 711206, G06F 1316

Patent

active

059909145

ABSTRACT:
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. One of the feature flags is used as a Present Bit for a corresponding memory page. When the feature flag Present Bit is set, the memory page has been reserved in the physical memory for graphics data and an address translation may be carried out. When the feature flag Present Bit is clear, the memory page has not been reserved for graphics data in the physical memory and a determination must then be made whether to perform the translation or generate an error signal to the computer processor.

REFERENCES:
patent: 5664224 (1997-09-01), Davis
patent: 5812789 (1998-09-01), Diaz et al.

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