Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-02-11
2002-10-08
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C365S203000, C365S204000
Reexamination Certificate
active
06462584
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to amplifier circuits, and particularly to those amplifier circuits providing a tail current source coupled to the commonly-connected node of a differential transistor pair.
2. Description of Related Art
As is well known in the art, a basic differential amplifier configuration is advantageously implemented using a pair of transistors configured as a differential pair, and using a constant current source in the “tail” of the differential pair. For example, a pair of NMOS transistors form a differential transistor pair when their respective source terminals are connected in a common node, or common-source node, and their respective gate terminals are connected to respective input terminals (e.g., for receiving a differential input signal). As another example, a pair of bipolar transistors form a differential transistor pair when their respective emitter terminals are commonly-connected in a common-emitter node, and their respective base terminals are connected to respective input terminals. When using NMOS transistors in the differential transistor pair, a constant current source is frequently approximated by a single N-channel transistor with a DC bias voltage on its gate having a value which is less than the nominal common mode voltage of the two input signals connected to the gates of the differential pair. Such a configuration assumes that the current tail transistor remains saturated, which requires its drain voltage to exceed its gate voltage less a threshold. But in a traditional differential pair configuration, the drain voltage of the current tail transistor (assuming it's the same node as the common-source node of the differential pair) must be lower in voltage than the higher of the two input signals less a threshold voltage for any current to flow through either of the differential pair transistors.
As a result, it is exceedingly difficult to use a traditional NMOS differential pair, having threshold voltages optimized for operation of the remaining circuitry of the integrated circuit, to sense a signal having a very low common-mode voltage which approaches or is below the threshold voltage (relative to, for example, the lower power supply voltage). To achieve such a low common mode input voltage, designers may use a PMOS differential pair biased toward an upper power supply. Such a PMOS differential transistor pair is usually slower than an NMOS pair, and also suffers from an analogous problem when presented with an input signal having a high common mode voltage which approaches (e.g., within a PMOS threshold voltage) the upper power supply voltage. As a result, designers frequently use both NMOS and PMOS differential transistor pairs, each connected to receive the differential input signal, with the currents through each pair summed to produce an output signal. Each of these techniques frequently adds complexity, degrades performance, or results in unwanted amplifier characteristics.
SUMMARY OF THE INVENTION
To afford the capability of sensing an input differential signal having a low common mode voltage when using, for example, an NMOS differential transistor pair, a current source device and a capacitor may be employed to provide at the common node of the differential transistor pair what appears to be a constant current source connected to a “negative voltage.”
In one embodiment particularly useful when using NMOS transistors in a differential transistor pair, one terminal of a capacitor (e.g., an MOS transistor configured as a capacitor) is precharged to VDD and the other terminal is precharged to VSS. When the amplifier needs to sense its differential input signal, a control signal turns off precharge transistors and couples the capacitor terminal previously at VSS to the common-source node of a differential transistor pair. The capacitor terminal previously precharged to VDD is driven toward VSS, preferably using a controlled current source, which couples the common-source node of the differential transistor pair from VSS toward a voltage below VSS. As soon as the common-source node voltage is low enough for at least one side of the differential pair to conduct a current substantially equal to that of controlled current source, the common source node voltage is substantially clamped at that voltage. The actual voltage resulting on the common-source node depends on the transistor characteristics, the particular voltages present on the gates of the differential pair, and the magnitude of the controlled current source. For some operating conditions, this voltage may be above ground rather than below ground, but the “tail” current of the differential pair nonetheless remains equal to the magnitude of current through the device driving the other end of the capacitor from VDD toward VSS.
No device configured to function as a constant current source is needed between the differential transistor pair and the capacitor because the tail current of the differential transistor pair is controlled by and substantially equal to the current discharging the other end of the capacitor, which current flows through the capacitor as a displacement current. If the discharging current is a constant current, the tail current is also a constant current. In this example, discharging a node previously precharged to VDD with a constant current toward VSS may be accomplished using straightforward circuits, such as an NMOS switch transistor in series with an NMOS current mirror transistor.
In a broader embodiment of the invention useful in an integrated circuit including a differential transistor pair having a common node connecting a respective first current handling terminal of each transistor within the pair, a method of providing a tail current for the differential transistor pair includes: (1) precharging a capacitive device having a first terminal and a second terminal; (2) providing a current path from the common node of the differential transistor pair to the first terminal of the capacitive device; and (3) driving, with a first current, the voltage of the second terminal of the precharged capacitive device in a direction to capacitively couple the first terminal and, by way of the current path, the common node to respective voltages sufficient in magnitude and polarity to cause a current, substantially equal to the first current, to flow collectively through one or both transistors of the differential transistor pair; (4) wherein the first current flows as a displacement current through the capacitive device and is projected onto the common node, thereby providing a dynamic tail current for the differential transistor pair substantially equal in magnitude to the first current.
For certain values of input voltages applied to the differential transistor pair, certain transistor characteristics of the differential transistor pair, and certain magnitudes of the first current, the first terminal of the capacitive device may assume a voltage outside a range of voltages bounded by the highest power supply voltage and the lowest power supply voltage operably received by the integrated circuit. In other cases, the first terminal of the capacitive device may assume a voltage within the range of voltages bounded by the highest power supply voltage and the lowest power supply voltage. In certain embodiments, the capacitive device is disposed in close local proximity to, and uniquely associated with, the differential transistor pair. In other embodiments, the capacitive device is disposed in close local proximity to, and also uniquely associated with, two separate differential transistor pairs, and each differential transistor pair may include a respective gating circuit connecting the respective common node thereof to the first terminal of the capacitive device. In certain embodiments, the connection path consists of a direct wired connection between the common node and the first terminal of the capacitive device, or, for other embodiments, may include at least one transistor connecting the common node
Integrated Device Technology Inc.
Lam Tuan T.
Nguyen Hiep
Zagorin O'Brien & Graham LLP
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