Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2005-08-11
2011-12-20
Vicary, Keith (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S244000
Reexamination Certificate
active
08082423
ABSTRACT:
A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a central collection point to re-distribute the flush signals to the execution units. Each unit generates a flush vector to all other execution units which is used to block register updates for the flushed instructions.
REFERENCES:
patent: 5913049 (1999-06-01), Shiell et al.
patent: 6282636 (2001-08-01), Yeh et al.
patent: 6598156 (2003-07-01), Arora
patent: 6728865 (2004-04-01), Coon et al.
patent: 2004/0244000 (2004-12-01), Frank et al.
Abernathy Christopher Michael
Feiste Kurt Alan
Ray David Scott
Shippy David
Van Norstrand, Jr. Albert James
International Business Machines - Corporation
Talpis Matthew B.
Vicary Keith
Yee & Associates P.C.
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