Generalized performance power optimized PLA circuits

Details Generalized performance power optimized PLA circuits Generalized performance power optimized PLA circuits

1977-08-31

1979-02-20

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307207, 307251, 307304, 364716, 365104, 365194, H03K 1728, H03K 1908, H03K 1920, G11C 1704

Patent

active

041409213

ABSTRACT:
An array of parallel FET load circuits on an IC (integrated circuit) chip can have their respective signal delays equalized where their nodal capacitances are different or alternately can have their signal delays set for different durations to meet the needs of a subsequent circuit, by adjusting the current driving capacity of a driver driving each circuit to meet the desired delay requirements thereof.

REFERENCES:
patent: 3974366 (1976-08-01), Hebenstreit
patent: 3993919 (1976-11-01), Cox et al.
patent: 4016431 (1977-04-01), Henle et al.
Delahanty et al., "PLA Driver with Integral Race Prevention," IBM Tech. Discl. Bull., vol. 19, No. 1, pp. 152-153, 6/1976.
Goertzel et al., "Automatic Power Minization and Delay Assignment for Semiconductor Circuits," IBM Tech. Discl. Bull., vol. 15, No. 6, pp. 2024-2025, 11/1975.
Leininger, "Designing Internal Delays in Large Scale Integrated Circuit Chips," IBM Tech. Discl. Bull., vol. 15, No. 2, pp. 421-422, 7/1972.

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