Generalized hierarchical architecture for bus adapters

Details Generalized hierarchical architecture for bus adapters Generalized hierarchical architecture for bus adapters

1992-03-27

1994-04-19

Fleming, Michael R.

Boots, shoes, and leggings

3642304, 3642405, 364DIG1, 3649424, 36493144, 36492691, 364DIG2, G06F 1314

Patent

active

053054423

ABSTRACT:
A top state controller controls a bus adapter to a selected master or slave top state in response to a command on a local or system bus during a dispatch state of the bus adapter. The bus adapter remains in the selected top state until the command is completed or suspended, whereupon it returns to the dispatch state. The top state controller sets a first flag upon a change from a master top state to the dispatch state in response to suspension of a command by a data handling device, and sets a second flag upon a change from a slave top state to the dispatch state upon completion of a command. The top state controller is responsive to the first or second flag to operate the bus adapter to that master top state from which the bus adapter changed to set the first flag and is responsive to the completion of the suspended command to clear the first and said second flags. The controlled bus adapter and top state controller permit resolution of deadlock conditions and establish priorities between the local and system buses, and permit suspension of the master states to respond to slave commands.

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