Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
Patent
1998-10-13
1999-12-21
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing architecture
Distributed processing system
712 1, 712 32, 709200, G06F 900
Patent
active
060063181
ABSTRACT:
A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor. The general purpose, programmable media processor is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams. Parallel general purpose media processors are disposed throughout the network in a distributed virtual manner to allow for multi-processor operations and sharing of resources through the network. A method for receiving, processing and transmitting media data streams over the communications fabric is also provided.
REFERENCES:
patent: 4893267 (1990-01-01), Alsup et al.
patent: 4975868 (1990-12-01), Freerksen
patent: 5201056 (1993-04-01), Daniel et al.
patent: 5268855 (1993-12-01), Mason et al.
patent: 5426600 (1995-06-01), Nakagawa et al.
IEEE Draft Standard for "Scalable Coherent Interface-Low-Voltage Differential Signal Specifications And Packet Encoding", IEEE Standards Department, P1596.3/D0.15 (Mar. 1992).
IEEE Draft Standard for "High-Bandwidth Memory Interface Based on SCI Signaling Technology (RamLink)", IEEE Standards Department, Draft 1.25 IEEE P1596.4-199X (May 1995).
Gerry Kane et al., "MIPS RISC Architecture", Prentice Hall (1995).
IBM, "The PowerPC Architecture: A Specification For A New Family of Risc Processors", 2nd Ed., Morgan Kaufmann Publishers, Inc., (1994).
Hewlett-Packard Co., "PA-RISC 1.1 Architecture and Instruction Set", Manual Part No. 09740-90039, (1990).
MIPS Computer Systems, Inc., "MIPS R4000 User's Manual", Mfg. Part No. M8-00040, (1990).
Hansen Craig C.
Moussouris John
An Meng-Ai T.
MicroUnity Systems Engineering, Inc.
Monestime Mackly
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