Dynamic magnetic information storage or retrieval – Converting an analog signal to digital form for recording;...
Reexamination Certificate
2002-10-08
2003-06-03
Faber, Alan T. (Department: 2651)
Dynamic magnetic information storage or retrieval
Converting an analog signal to digital form for recording;...
C360S051000, C360S046000, C375S354000, C341S155000
Reexamination Certificate
active
06574059
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit and a method of determining a most probable bit sequence represented by an analog waveform received through a communication channel.
2. Background Art
Current read channels use a variety of methods and circuits to detect a bit sequence transmitted from a source, or read from a medium. State of the art systems use error control coding to encode running blocks within the bit sequence prior to transmitting/recording the resulting data. At the receiving/reading end, a detector operates on a running block of the data to extract the encoded bit sequence. The encoded bit sequence is then decoded to produce the original bit sequence. This method allows the bit sequence to be distinguished from noise that may be introduced in the communication channel or in the storage media.
Popular circuits used in the communications field and the digital storage field are a convolution encoder and a Viterbi decoder (often called a “trellis decoder.”) The convolution encoder maps “k” input bits into “n” transmission/recording bits producing a “k
” rate code bitstream. Variable “k” is called a constraint length of the code. Values for constraint length “k” may range from two and up, with k=7 being the present industrial standard. Rate codes typically range from ½ to {fraction (16/17)}, with ½ and ⅓ rates commonly used in the communications field and higher rates commonly used in the digital storage field.
The Viterbi decoder operates on the received/read bits in multiple steps to determine the original input bits. As each new bit is received, the Viterbi decoder calculates an error probability for each transition between the prior possible sequences of bits received and the current possible sequences of bits received. The error probabilities form a trellis having multiple paths that branch with each new bit received. By summing the probable errors along each path of the trellis from a finite bit in the past to the new bit received, a path with the lowest cumulative error may be found. The Viterbi decoder then determines the most likely sequence of input bits from this lowest-error path. Longer lowest-error paths result in higher probability that the decoded bits are error free.
Limitations of Viterbi decoders are their ability to work with high speed data in real time and their ability to adapt to new algorithms. The Viterbi decoding algorithm requires a large number of computations for each new bit received. For high data rate read channels and/or long constraint lengths, these computations must be performed in high speed hardware circuits. Software programs executing in general purpose processors cannot meet the throughput requirements of high demand read channels. Dedicated Viterbi decoder integrated circuits are available commercially that can operate at data rates of up to 30 Mbps. However, these chips provide the read channel designer with a limited number of options for the actual decoding algorithm. Major change to the decoding algorithm require a complete redesign of the integrated circuits to implement the new algorithm.
SUMMARY OF THE INVENTION
The present invention is a method and a circuit for determining a bit sequence from an analog waveform representing the bit sequence, and at least one other parameter associated with the analog waveform. The method includes periodically converting the analog waveform and the at least one other parameter associated with the analog waveform into digital numbers. Both resulting digital numbers are concatenated to create an address used periodically to look up a bit from an array of bits stored in a memory. The stored bits are predetermined to be the most likely bit for each possible address. Finally, one addressed bit is output each period to form the bit sequence.
The other at least one parameter digitized for use as part of the address may vary depending upon the needs of the application. One possible other parameter is the average amplitude of the waveform envelope proximate to the current bit being detected. Another possible other parameter is the absolute amplitude of the waveform itself one or more bit cells ahead of and/or behind the current bit begin detected. Where the analog waveform is being read from a recoding media, the other parameter may include the velocity of the media moving past the read head. With tape media, the other parameter may also be the tension of the tape across the read head.
The at least one other parameter may be filtered and/or delayed in time as necessary. Filter types include an averaging filter to minimize the effects of minor fluctuations in the at least one other parameter. Time delays may also be applied to the current bit being detected to account for any latencies in the at least one other parameter.
A circuit that implements the present invention requires at least one analog to digital converter, two registers, a controller and a read-only memory containing the predetermined most likely bits stored by address. The at least one analog to digital converter is used to convert the analog waveform and the at least one other parameter into digital form. The registers store the resulting digital numbers so that they are available simultaneously. Outputs from the registers are connected to the address input of the read-only memory. The controller provides timing commands for the at least one analog to digital converter and the registers based upon an external clock signal synchronized to the analog waveform. As each new address is presented to the read-only memory, the appropriate bit is output from the read-only memory thereby forming the bit sequence.
The circuit may contain a filter between the at least one analog to digital converter and the appropriate register to average the at least one other parameter. A series of shift registers may be included to time delay the current bit being detected to synchronize with other parameters converted later.
Accordingly, it is an object of the present invention to provide a method for determining a bit sequence from an analog waveform encoding the bit sequence and at least one other parameter associated with the analog waveform. The method includes a look up function to find the most likely bits in the bit sequence from among a set of predetermined most likely bits.
Another object of the present invention is to provide a circuit that determines a bit sequence from an analog waveform representing the bit sequence, at least one other parameter associated with the analog waveform, and a clock signal associated with the analog waveform. At the core of the circuit is a read-only memory storing a set of predetermined most likely bits as a function of an address.
These and other objects, features and advantages will be readily apparent upon consideration of the following detailed description in conjunction with the accompanying drawings.
REFERENCES:
patent: 5136290 (1992-08-01), Bond et al.
patent: 5262907 (1993-11-01), Duffy et al.
patent: 5973626 (1999-10-01), Berger et al.
Brooks & Kushman P.C.
Storage Technology Corporation
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