General purpose decode implementation for multiported memory...

Details General purpose decode implementation for multiported memory... General purpose decode implementation for multiported memory...

2000-02-21

2001-02-06

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S230060

Reexamination Certificate

active

06185148

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to integrated circuits and in particular to a decoder for enabling a portion of a memory array.
BACKGROUND
Various decoder schemes may be used to enable portions of memory in a memory array. A word line decoder generates a word line signal to activate (or enable) a quantity (e.g., a word) of memory within a memory bank. A bank may have numerous words and thus require numerous (e.g., 16) decoders. Each decoder produces a word line signal to enable the word for the implementation of either a store (write) or load (read) operation for a selected word of the memory bank. In doing so, it receives various store enable and load enable signals and generates the word line signal when either a store or load operation is to be performed.
FIGS. 1A and 1B
show a traditional word line decoder circuit
50
. Decoder circuit
50
receives fully dynamic, full-phase store and load enable signals (STEN
0
, STEN
1
, STEN
2
, LDEN
0
, and LDEN
1
) from store and load sources SS
0
, SS
1
, SS
2
, LS
0
, and LS
1
, respectively. These signals are triggered from the rising edge of a clock (CLK) signal. Decoder circuit
50
generates a word line enable signal (WL) if either all of the store enable or all of the load enable signals are true (e.g., high) at the same time when the clock is in its first phase (high).
One or more gates are depicted in the store and load source blocks to indicate their delay (in terms of gate delay) from the clock=s rising edge. Several gate delays can occur within a single phase of the clock single. That is, signals may occur at different points within the active (e.g., high) phase of the clock, but they all occur within that phase. In
FIG. 1
, the store enable signals, STEN
0
, STEN
1
, and STEN
2
, are delayed by one, two, and three gate delays from the clock's rising edge. In contrast, the load enable signals, LDEN
0
and LDEN
1
, are both only delayed by one gate delay from the rising edge.
Circuit
50
includes a store decode section
60
, a load decode section
70
, and an output section
80
. Store decode section
60
includes transistors Q
1
through Q
8
; the load section includes transistors Q
9
through Q
15
; and the output section includes transistors Q
16
through Q
22
. Transistors Q
1
, Q
6
, Q
7
, Q
9
, Q
13
, Q
14
, Q
16
, Q
20
, and Q
21
are PFET type transistors, and the remaining transistors are NFET type transistors.
Store section
60
is configured as a precharged AND gate with inputs at STEN
0
-STEN
2
, and an output at ST. Q
1
through Q
5
are connected in a stacked NAND precharge circuit configuration. Q
1
is a precharge transistor, Q
5
is an evaluate transistor, and Q
2
through Q
4
are the NAND input transistors making up the stack for receiving the STEN
0
, STEN
1
, and STEN
2
signals, respectively. The clock (CLK) signal is connected to the gates of precharge transistor Q
1
and evaluate transistors Q
5
. The drain of precharge transistor Q
1
defines the precharged node, which is labeled NST, and is connected to the drain of Q
2
. Transistors Q
7
and Q
8
are configured as a conventional static inverter that has its input connected to the NST node and its output, which is labeled ST, defining the output node for the store section
60
. Transistor Q
6
serves as half-latch for holding up the NST node when the ST node goes Low.
The load section
70
is also configured as a precharge AND gate with inputs at LDEN
0
and LDEN
1
, and an output at LD. Q
9
-Q
12
form a precharged NAND stack having a precharged node at NLD. Q
9
and Q
12
are the precharge and evaluate transistors, respectively, with the clock signal connected to their gates. Q
11
and Q
12
serve as the NAND stack input transistors receiving the input LDEN
0
and LDEN
1
load enable signals, respectively. Q
14
and Q
15
form a static inverter having its input connected to the NLD node and an output providing the LD output node. With its drain connected to the NLD node and its gate connected to the LD node, Q
13
serves as half-latch for holding up the NLD node when the LD node is low.
Output section
80
performs an OR function with its inputs being the ST and LD signals and its output being the word line (WL) signal. Q
16
-Q
19
are connected in a precharge OR circuit configuration. Q
16
and Q
19
are precharge and evaluate transistors, respectively, with their gates connected to the clock signal. Q
17
and Q
18
are in a conventional NOR configuration with their commonly connected drains connected to the drain of precharge transistor Q
16
and their commonly connected sources connected to the drain of evaluate transistor Q
19
. The gate of Q
17
is connected to the LD node, and the gate of Q
18
is connected to the ST node. Their commonly connected drains define the precharged node labeled NWL. Transistors Q
21
and Q
22
are connected in a conventional static inverter arrangement with the input connected to the NWL node and the output providing the WL node, which is the output of the decoder circuit
50
. Q
20
functions as half-latch with its drain connected to the NWL node for holding it up when the WL node is low.
With regard to the operation of the store section
60
, during a precharge state, (when the clock is low), Q
1
is turned on and Q
5
is off. This causes node NST to precharge to a high value without regard to the values of STEN
0
-STEN
2
. Thus, during the precharge state, the Q
7
/Q
8
inverter output at ST is low. When the clock transitions to a high (during an evaluate state), Q
1
turns off and Q
5
turns on. If all of the STEN
0
, STEN
1
, and STEN
2
signals are true (or high) at the same time, node NST is discharged low, which causes ST to go high. Conversely, if any of these store enable signals are false (or low), the NST node remains charged high, and the ST output remains low. Accordingly, when STEN
0
, STEN
1
,and STEN
2
are all high at the same time in an evaluate state, NST goes low and ST goes high indicating that a store operation is to occur.
The load section
70
functions in the same way. If LDEN
0
and LDEN
1
are high at the same time during an evaluate state (when CLK is high), the NLD node discharges and goes low. This causes the LD node to go high indicating that a load operation is to occur. Conversely, if any of LDEN
0
or LDEN
1
are not true, the NLD node remains charged high, and the LD node remains at a low value.
With regard to the output section
80
, precharge transistor Q
16
and evaluate transistor Q
19
operate to precharge the NWL node during the precharge (clock low) state. During the evaluate state, if either ST or LD are high, node NWL is discharged low, which causes WL to go high. This corresponds to a word line activation. If neither ST or LD are high during the evaluation state, the WL node remains low, and the word line is not fired.
Unfortunately, there are several problems associated with this decoder solution. To begin with, circuit
50
uses fully clock dynamic gates for each of the decoder sections. That is, each of the sections has precharge and evaluate transistors that are continuously drawing clock power in their respective states. This clock loading problem is exaggerated in typical applications that require numerous word line decoders (e.g., 16, 32) for each memory bank. In addition, with a three input NAND stack in the store decoder section, the Q
2
-Q
4
NFETs must be excessively large in order to operate sufficiently fast for most present-day applications. Moreover, the dynamic NAND inputs (at Q
2
-Q
4
and Q
10
-Q
11
) can be especially sensitive to noisy inputs. This can be problematic—especially when some (or all) of the store enable and/or load enable signals are received from distant sources within a system such as a microprocessor. For example, with the decoder of
FIG. 1
, the STEN
0
and LDEN
0
signals are received from first-stage decoder sources that are 1200 microns away from the decoder circuit
50
.
Accordingly, what is needed is an improved decoder scheme that will solve any or all of these problems.
SUMMARY OF THE

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