Image analysis – Image transformation or preprocessing – General purpose image processor
Reexamination Certificate
1998-02-18
2001-09-11
Couso, Jose L. (Department: 2724)
Image analysis
Image transformation or preprocessing
General purpose image processor
C382S308000
Reexamination Certificate
active
06289138
ABSTRACT:
Microfiche Appendix: There are 2 microfiche in total, and 101 frames in total.
FIELD OF THE INVENTION
The present invention relates to an image processor and more particularly to a high speed, reusable image processor capable of performing many image processing operations.
BACKGROUND OF THE INVENTION
Image processing is usually performed by a host computer, with all the arithmetic operations normally done in software. However, as the demand on throughput increases, it is usually necessary to process an image using special-purpose image processors. These image processors typically incorporate hardware that accelerates arithmetic operations, thereby increasing the throughput. It is also usually desirable or necessary for these image processors to be able to perform many kinds of image processing operations, including compositing, color space conversion, image transformation, convolution, halftoning and so on.
One method of implementing hardware for general image processing is by implementing various sub-blocks within the image processor, each of which is capable of performing one of the functionalities required. However, this method requires a lot of hardware and hence can be very expensive to implement. Hardware implemented by this method also cannot be configured to perform image processing operations other than those that are specified originally.
Another method of implementing hardware for general image processing is to implement a data path that is able to perform some basic functionalities, and control logic that can perform a predetermined sequence of operations on the image to achieve the desired image processing function. This method, however, is usually too slow when the demand on the throughput is high. Hardware implemented by this method also cannot be configured to perform other image processing operations.
Both methods described above also usually require a very complicated design to perform the required image processing operations. Hence usually the cost of designing such an image processor is large. Therefore, a need clearly exists for an image processor capable of performing many image processing operations that is able to overcome one or more of the disadvantages of conventional devices.
SUMMARY OF THE INVENTION
In accordance with a first aspect of the invention, there is provided an apparatus for performing image processing operations on data objects, the apparatus including:
data source circuitry for providing a stream of the data objects;
a plurality of operand source circuits for providing streams of operand objects, or providing operand objects in response to an address presented;
instruction circuitry for selecting an image processing operation, and enabling or disabling a plurality of options in the image processing operation;
a configuration register for storing the image processing operation and options;
a register file for storing information necessary for performing the image processing operation;
decoding circuit connected to the configuration register for decoding the image processing operation and options;
a control signal register connected to the decoding circuit for storing the output of the decoding circuit;
input interface circuitry, connected to the control signal register, the register file, the data source circuit and the plurality of the operand source circuitry, for:
(a) accepting, storing and rearranging the data objects from the data source circuit, and the operand objects from the operand source circuit, in accordance with the output of the control signal register,
(b) generating addresses for the operand objects, in accordance with the output of the control signals register and the register file, and
(c) updating the information in the register file to reflect a current status of the image processing operation;
processing circuitry, connected to the input interface circuit, the register file, and the control signal register, for performing arithmetic operations on the output of the input interface circuit in accordance with the output of the control signals register and the register file to produce processed data objects; and
data destination circuitry connected to the processing circuitry for receiving the processed data objects.
Preferably, the processing circuit further includes: a plurality of identical channel processing circuits for performing the arithmetic operations on part of the output of the input interface circuit in accordance with the output of the control signal register and the register file; and flow control circuitry connected to the plurality of the channel processing circuit for controlling a flow of the data objects in the channel processing circuit by outputting enable signals in accordance with the output of the control signal register.
Optionally, the channel processing circuit further includes: a plurality of identical arithmetic units connected to the flow control circuit for performing the arithmetic operations on the data objects in accordance with the output of the control signal register; combining circuit, connected to the flow control circuit and the arithmetic units, for adding the outputs of a plurality of the arithmetic units and the register file in accordance with the output of the control signal register and the register file; first post-processing circuit, connected to the combining circuit and the flow control circuit, for rounding an output of the combining circuit, finding the absolute value of the rounded output, and clamping of the absolute value in accordance with the output of the control signal register; second post-processing circuit, connected to a selected plurality of arithmetic units and the first post-processing circuit, for selecting between the outputs of the arithmetic units and the first post-processing circuit and clamping the selected output, if necessary, in accordance with the output of the control signal register; and routing logic, connected to a plurality of the arithmetic units, the combining circuit and the first post-processing circuit, for routing selected outputs of a plurality of the arithmetic units and the first post-processing circuit to selected inputs of a plurality of the arithmetic units and the combining circuit. Optionally, the number of the channel processing circuits in the processing circuit is four.
In accordance with a second aspect of the invention, there is provided an apparatus for performing compositing between two streams of pixels and a stream of attenuation values, the apparatus including:
data source circuitry for providing a first one of the streams of pixels;
first operand source circuitry for providing a second one of the streams of pixels;
second operand source circuitry for providing the stream of attenuation values;
an instruction circuit for enabling or disabling a plurality of options in compositing operations;
a configuration register for storing a compositing operation and the options of the instruction circuit;
register file for storing information necessary for performing compositing operations;
a decoding circuit connected to the configuration register for decoding the options and the compositing operation;
a control signal register connected to the decoding circuit for storing the output of the decoding circuit;
an input interface circuit, connected to the control signal register, the register file, the data source circuit, the first operand source circuit and the second operand source circuit, for:
(a) accepting, storing and rearranging pixels from the data source circuit and the first operand source circuit, and attenuation values from the second operand source circuit in accordance with an output of the control signal register,
(b) generating a stream of data objects to replace the second stream of pixels from the first operand source in accordance with the output of the control signal register and the register file, and
(c) updating the information in the register file to reflect a current status of the compositing operation;
processing circuitry, connected to the input interface circuit, the register file, and the control
Gibson Ian
Pulver Mark
Yip Dominic
Canon Kabushiki Kaisha
Couso Jose L.
Do Anh Hong
Fitzpatrick ,Cella, Harper & Scinto
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