General finite-field multiplier and method of the same

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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06925479

ABSTRACT:
A general finite-field multiplier and the method of the same are disclosed for the operation of the finite-field multipliers of various specifications. In the multiplier, AND gates and XOR gates are used as primary components, and the inputs include two elements A and B to be multiplied and the coefficients of a variable polynomial p(x). This multiplier can be applied to the finite-field elements of different bit number. After all the coefficients of the A, B and p(x) are input, the values of a desired C can be obtained rapidly. Since the output values are parallel output, the application is very convenient. Furthermore, the multiplier can be used in the RS chip for different specifications.

REFERENCES:
patent: 5680340 (1997-10-01), Glover et al.
patent: 5887006 (1999-03-01), Sharma
patent: 6178436 (2001-01-01), Blake et al.
patent: 6343305 (2002-01-01), Koç et al.
patent: 6389442 (2002-05-01), Yin et al.
patent: 6701336 (2004-03-01), Shen et al.

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