GE-SI SOI MOS transistor and method of fabricating same

Details GE-SI SOI MOS transistor and method of fabricating same GE-SI SOI MOS transistor and method of fabricating same

1994-06-10

1998-03-10

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

257 63, 257 65, 257 66, H01L 2904, H01L 31036, H01L 310376, H01L 3120

Patent

active

057264597

ABSTRACT:
A Ge--Si MOS transistor for high speed, high density applications in which a thin layer of silicon (Si) is doped to have a concentration of germanium (Ge) ions which is preferably between 10 and 30%. The germanium doped silicon is formed on a layer or substrate of insulator. Optional silicidation of the drain and source regions improves conductivity therein and the use of shallow SIMOX processing technologies results in a more cost-effective and rapid fabrication process.

REFERENCES:
patent: 4740829 (1988-04-01), Nakagiri et al.
patent: 5475244 (1995-12-01), Koizumi
IBM Tech Disc Bulletin, vol. 35 No. 2, Jul. 1992, pp. 468-469.

Affiliated with

Also associated with

Rating

GE-SI SOI MOS transistor and method of fabricating same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with GE-SI SOI MOS transistor and method of fabricating same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and GE-SI SOI MOS transistor and method of fabricating same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-141929