Gating circuit with spurious signal prevention means

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

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Details

307243, 307518, 307470, 307311, H03K 1756, H03K 1920

Patent

active

044940130

DESCRIPTION:

BRIEF SUMMARY
This invention relates to a gating circuit for applying an output signal to one of a plurality of output lines in response to an incoming signal being applied to one of a plurality of input lines.
In many process control situations it it desirable to monitor a plurality of operating parameters of the process and to give a warning or initiate a shutdown of the process if any one of the operating parameters reaches a dangerous level or otherwise indicates that a fault has arisen.
An object of the present invention is to provide a gating circuit that can provide an output signal in response to any one of a plurality of input signals being received while having a low probability of being triggered by a spurious input signal.
According to the present invention there is provided a gating circuit including: a plurality of monitoring input lines each of which is arranged to receive an input signal of predetermined minimum duration in response to a predetermined change of condition of an externally monitored parameter; a main gate coupled to the monitoring input lines and having a plurality of output lines, a respective one output line being provided for each monitoring input line, the main gate also including an enabling input and being operable when an enabling signal is applied to said enabling input to apply a signal to the respective output line in response to said input signal of minimum duration being applied to one of the monitoring input lines; an input signal verifier circuit including a plurality of verifier input lines each coupled to a respective one of the monitoring input lines, the verifier circuit also including a verifier gate arranged to receive a direct gate input signal when any one of the monitoring input lines has said minimum duration input signal thereon and to receive a delayed gate input signal after a predetermined time delay less than said minimum duration when any monitoring input line has said input signal thereon, the verifier gate having a verifier output line coupled to said enabling input, the verifier gate being operable to provide said enabling signal on said verifier output line if, and only if, the direct and delayed gate input signals are being received thereby simultaneously.
The minimum duration input signal is preferably a continuous signal.
The main gate preferably comprises a latch circuit having a clock input terminal consitituting the enabling input, the latch circuit including a plurality of positive edge triggered D-type flip-flops each of which is operable to latch an input to a corresponding output when the enabling signal is applied to the clock input terminal.
The verifier circuit preferably further includes a verifier input gate having the verifier input lines coupled thereto and having an output coupled to the verifier gate both directly and through delay means, the verifier input gate being operable to provide an output signal at the output thereof when any one of the monitoring input lines has a signal thereon.
The gating circuit may further include a locking means operable to supply a continuous disabling signal to the enabling input when any output line has a signal applied thereto by the main gate so that only the first input appearing on a monitoring input line is passed to the main gate output line.
A reset means may be provided and operable to supply a reset signal to the enabling input to enable the main gate to be reset after any minimum duration input signal has been applied to a respective main gate output line.
A preferred embodiment of a gating circuit according to the present invention is illustrated in the accompanying drawing and reference will be made to the drawing in the following description.
The gating circuit illustrated includes a plurality of monitoring input lines 10 each of which is arranged to receive an input signal of predetermined minimum duration in response to a predetermined change of condition of an externally monitored parameter. For example, in use each input 10 could be provided with an input signal if a respective paramete

REFERENCES:
patent: 3191067 (1965-06-01), Zimmerman
patent: 3234534 (1966-02-01), Todman
patent: 3289193 (1966-11-01), Worthington et al.
patent: 3758867 (1973-09-01), Schulz
patent: 3769606 (1973-10-01), Henegar
patent: 3771130 (1973-11-01), Moses
patent: 4214213 (1980-07-01), Ferrie

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