Gating circuit for analog values

Details Gating circuit for analog values Gating circuit for analog values

1999-09-30

2001-02-20

Cunningham, Terry (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S094000, C327S560000

Reexamination Certificate

active

06191639

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to gating circuits. More particularly, this invention pertains to a gating circuit for analog values obtained in a predetermined sequence, capacitively buffer-stored, digitized by means of an A/D converter and subsequently erased, by discharge of the capacitive store within a time interval that is predetermined by a gating pulse, before the next analog signal is obtained.
2. Describing the Prior Art
Many measured-value processing circuits obtain an analog measured or signal value in a specific (e.g. periodic) sequence that is cumulatively stored or buffer-stored during a specific period of time and then subject to analog/digital conversion for further processing as a digital value. An example of a measurement system of this type, with either open or closed control loop, is the fiber-optic gyro (FOG), the fundamental structure of which is illustrated in FIG.
4
. In such a device, light from a light source
30
is directed, via an optical waveguide, to a coupler
31
(e.g. a 2×2 coupler). The coupled signal propagates in the opposite direction, via another optical waveguide, to a photosensitive detector
34
. Proceeding in the forward direction, a polarizer and a beamsplitter are connected to an output of the coupler
31
via still another optical waveguide designed, for example, as a space domain filter with polarizer and beam-splitter combined in a multifunctional integrated optical chip (MIOC)
32
. In such a case, a phase modulator can also be integrated within the MIOC
32
. Incoming light is split into two approximate halves in the beamsplitter of the MIOC
32
. As a result, two partial waves penetrate in opposite directions an optical waveguide in the form of a fiber coil
33
connected to the two outputs of the MIOC
32
. After passing through the coil
33
, the partial waves are reunited in the beamsplitter of the MIOC
32
, then pass through the polarizer and the above-mentioned space domain filter to the coupler
31
. From there they pass to the detector
34
, whose output signal, in the downstream signal processing path, is initially amplified in an amplifier
4
and then cumulatively stored in a capacitive store that may be part of a low-pass filter. In this way, the output signal can be subsequently subjected to analog/digital conversion as a momentarily cumulated signal value by an A/D converter
5
. Digital values from the A/D converter
5
are fed to a digital signal evaluation and control circuit
35
. In the case of a FOG with a closed control loop, analog resetting is affected in the MIOC
32
via an A/D converter
36
. At approximately the same time, the digital evaluation and control circuit
35
supplies a gating pulse whose function will be discussed below (in connection with FIGS.
2
and
3
).
In the case of the measuring device described with reference to
FIG. 4
, gating is done to generate the signal value (generated during a measurement cycle or loop) after the A/D conversion with as few glitches as possible. That is, with as few as possible voltage spikes being produced by the gating operation and capable, on average, of shifting the start value of the A/D converter. Difficulties, described with reference to
FIG. 2
, illustrating a solution of the prior art, arise in this process.
Referring to
FIG. 2
, a circuit schematic of a gating circuit for minimizing glitches when generating a signal value after A/D conversion in accordance with the prior art, the signal from the amplifier
4
passes to the input of the A/D converter
5
via a low-pass filter comprising a resistor
1
and a capacitor
2
. The upper signal profile illustrated in
FIG. 3
shows, at the left hand part, the profile of potential that builds up at point A. The cumulated signal value is applied to the input of the A/D converter
5
within a specific time slot designated by the signal STARTCONVERT
37
. After A/D conversion, a switch
3
(governed by a gating pulse at
9
) that bridges the capacitor
2
is closed. As a result, all information from the relevant loop is erased in the capacitor
2
. At the reference-earth point of the capacitive store (i.e. of the capacitor
2
) a DC voltage required for the A/D converter
5
is set by means of a buffer
6
and RC elements
7
and
8
.
The circuit described thus far with reference to
FIG. 2
faces a crucial problem. Under specific boundary conditions, the amplitude of the gating pulse at the terminal
9
must reach a considerable value (e.g. up to 12 V) to be capable of reliably short-circuiting the capacitor
2
. This is not consistent with supplying the circuit with just 5 V. The reasons for this can be found in the required offset for the A/D converter
5
and in the level of the gate voltage for the FETs in the switch
3
for reliable and low-impedance switching. Due to the gating caused by the gating pulse at
9
, the signal profile at point A exhibits overshoots (i.e. the above-mentioned glitch) that can cause the above-mentioned undesirable shift of the start value of the next respective A/D conversion, in some instances as a function of the respective preceding signal value. Bipolar transistors, triggered by their base currents, would build an additional DC voltage potential across the capacitor
2
, bringing about the same effect as signal overshoots.
SUMMARY AND OBJECTS OF THE INVENTION
It is therefore an object of the present invention to provide a gating circuit for a measured value processing circuit which avoids problems associated with the gating operation concerning overshoots or glitches onto subsequent A/D conversions.
It is a further object of the invention to provide a gating circuit for a measured value processing circuit in which it is possible to approach a voltage near the supply voltage with the signals to be gated without any particular requirements on gating pulse amplitude.
The present invention addresses the preceding and other objects by providing an improvement in a gating circuit for analog signal values obtained in a periodic sequence, capacitively buffer-stored, digitized by an A/D converter and subsequently erased, before a next analog signal value is obtained, by discharge of the capacitive store within a time interval that is predetermined by a gating pulse. The improvement provided by the invention to such a gating circuit includes a first operational transconductance amplifier which can be activated by the gating pulse.
A non-inverting input of the first amplifier is connected to a reference-earth point of the capacitive store and its output is connected to a charging terminal of the capacitive store. An inverting input of the first amplifier is connected through an impedance converter and a discharge-current variable resistor to the charging terminal of the capacitive store.
A second operational transconductance amplifier is provided through which the analog signal values pass to the charging terminal of the capacitive store. The gain of the second amplifier is predetermined by the ratio of a resistor, connected in parallel with the capacitive store, to a series resistor that determines the potential at the inverting input of the second amplifier.
The preceding and other features and advantages of this invention will become further apparent from the detailed description that follows. Numerals of the written description correspond to those of drawing figures for illustrating the invention with like numerals referring to like features throughout.


REFERENCES:
patent: 4404479 (1983-09-01), Toyomaki
patent: 5479121 (1995-12-01), Shen et al.
patent: 5606277 (1997-02-01), Feliz
patent: 5774021 (1998-06-01), Szepesl et al.
patent: 0831495 (1998-03-01), None
patent: 2108343 (1983-05-01), None

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