Gated thyristor and related system and method

Details Gated thyristor and related system and method Gated thyristor and related system and method

2007-07-05

2009-11-17

Paladini, Albert W (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000, C361S118000

Reexamination Certificate

active

07619863

ABSTRACT:
An embodiment of a protection circuit, comprising a first PNP-type bipolar transistor and a second NPN-type bipolar transistor, the base of the first transistor being connected to the collector of the second transistor and the collector of the first transistor being connected to the base of the second transistor, in which a MOS transistor is connected between the collector and the emitter of the second transistor.

REFERENCES:
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patent: 6072677 (2000-06-01), Chen et al.
patent: 6538266 (2003-03-01), Lee et al.
patent: 6642088 (2003-11-01), Yu
patent: 2003/0141545 (2003-07-01), Okawa et al.
patent: 2004/0100746 (2004-05-01), Chen et al.
French No. 06/52837, Search Report; published Feb. 6, 2007.

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