Gated thyristor and process for its simultaneous fabrication wit

Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device

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Details

327428, 327429, 327439, 327440, 327442, H03K 1768, H03K 1760

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active

055044514

ABSTRACT:
An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (556/403); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (557, 405) for the gating of an EEPROM memory array or the like; a Fowler-Nordheim tunneling EEPROM cell (558); (n-) and (p-) channel drain-extended insulated-gate field-effect transistors (407, 560); vertical and lateral annular DMOS transistors (409, 561); a Schottky diode (411); and a FAMOS EPROM cell (562). A "non-stack" double-level poly EEPROM cell (676) with enhanced reliability (676) is also disclosed.

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patent: 4125787 (1978-11-01), Ohhinata et al.
patent: 4398205 (1983-08-01), Spellman et al.
patent: 4472642 (1984-09-01), Akamatsu
patent: 4572968 (1986-02-01), Petty
patent: 4665316 (1987-05-01), Hodges
patent: 5086242 (1992-02-01), Heilman et al.
patent: 5287014 (1994-02-01), Kinoshita

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