Patent
1996-12-23
2000-01-04
Beausoliel, Jr., Robert W.
39518504, G06F 1100
Patent
active
06011908&
ABSTRACT:
A gated store buffer including circuitry for temporarily holding apart from other memory stores all memory stores sequentially generated during a translation interval by a host processor translating a sequence of target instructions into host instructions, circuitry for transferring memory stores sequentially generated during a translation interval to memory if the translation executes without generating an exception, circuitry for indicating which memory stores to identical memory addresses are most recent in response to a memory access at the memory address, and circuitry for eliminating memory stores sequentially generated during a translation interval if the translation executes without generating an exception.
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D'Souza Godfrey P.
Wing Malcolm J.
Baderman Scott T.
Beausoliel, Jr. Robert W.
King Stephen L.
Transmeta Corporation
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