Gated parallel decoder

Details Gated parallel decoder Gated parallel decoder

1981-02-06

1983-08-09

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307562, 307575, 307603, 365230, H03K 19017, H03K 19094, G11C 800

Patent

active

043981020

ABSTRACT:
The decoder includes a plurality of input signal responsive transistors having their conduction paths connected in parallel between a node and a point of reference potential. These transistors, when turned-on, tend to clamp the node to the reference potential. A controllable load is connected between a second voltage and the node for, when enabled and in the absence of an inhibit signal, providing a conduction path charging the node towards the second voltage. An inhibit network responsive to the node voltage inhibits conduction via the charging conduction path of the load when the node voltage is at, or close to, the second voltage. An external control signal applied to the controllable load can enable it in the absence of the inhibit signal.

REFERENCES:
patent: 3959782 (1976-05-01), Dunn
patent: 3976892 (1976-08-01), Buchanan
Huffman et al., "Memory Address Decode Circuit", IBM Tech. Disc. Bull., vol. 19, No. 1, pp. 28-29, Jun. 1976.

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