Gated lateral thyristor-based random access memory cell...

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with other solid-state active device in integrated...

Reexamination Certificate

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C257S107000, C257S141000, C257S162000

Reexamination Certificate

active

07042027

ABSTRACT:
One aspect of the present subject matter relates to a memory cell, or more specifically, to a scalable GLTRAM cell that provides DRAM-like density and SRAM-like performance. According to various embodiments, the memory cell includes an access transistor and a gated, lateral thyristor integrally formed above the access transistor. The access transistor has a drain region, a raised source region, and a gate. The thyristor has a first end that is formed with the raised source region of the access transistor. In various embodiments, the lateral thyristor is fabricated using a metal-induced lateral crystallization technique (MILC) adopted for thin-film-transistor (TFT) technology. In various embodiments, the stacked lateral thyristor is integrated by raising the source region of the access transistor using a selective epitaxy process for raised source-drain technology. Other aspects are provided herein.

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