Gated integrator with signal baseline subtraction

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – By integrating

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327307, 327336, 327337, 330 9, 330 11, G06G 764

Patent

active

055857566

ABSTRACT:
An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window.

REFERENCES:
patent: 3818357 (1974-06-01), Crockett et al.
patent: 3953805 (1976-04-01), Couvillon
patent: 4119960 (1978-10-01), Hill
patent: 4211981 (1980-07-01), Lerma
patent: 4237424 (1980-12-01), Weiner
patent: 4257006 (1981-03-01), Schaumann
patent: 4365204 (1982-12-01), Haque
patent: 4393351 (1983-07-01), Gregorian et al.
patent: 4438354 (1984-03-01), Haque et al.
patent: 4651032 (1987-03-01), Nobuta
patent: 4800586 (1989-01-01), Meier
patent: 4814714 (1989-03-01), Beadle
patent: 5175748 (1992-12-01), Takahashi
Nowicka,"Differential Amp Cancels Integrator's Crosstalk" Electronics Dec. 18, 1980.
"Model SR250 Fast Gated Integrators and Boxcar Averager", Stanford Research Systems, Product Data Sheet.
"Gated Integrator Module", Evans Electronics, 1991.
"Bunch Signal Processor", Bergoz.

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