Gated delay-locked loop for clock generation applications

Details Gated delay-locked loop for clock generation applications Gated delay-locked loop for clock generation applications

1999-04-30

2001-03-27

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000, C327S244000, C327S248000, C327S277000, C327S299000

Reexamination Certificate

active

06208183

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to clock generation circuits and, more particularly, relates to a clock generation circuit utilizing a gated delay-locked loop architecture.
BACKGROUND OF THE INVENTION
Many electrical and computer applications and components have critical timing requirements that compel generation of periodic clock waveforms that are precisely synchronized with a reference clock waveform. A phase-locked loop (“PLL”) is one type of circuit that is widely used to provide an output signal having a precisely controlled frequency that is synchronous with the frequency of a reference or input signal. Wireless communication devices, frequency synthesizers, multipliers and dividers, single and multiple clock generators, and clock recovery circuits are but a few examples of the manifold implementations of PLLs.
Frequency synthesis is a particularly common technique used to generate a high frequency clock from a lower frequency reference clock. In microprocessors, for example, an on-chip PLL can multiply the frequency of a low frequency input (off-chip) clock, typically in the range of 1 to 4 MHz, to generate a high frequency output clock, typically in the range of 10 to over 200 MHz, that is precisely synchronized with the lower frequency external clock. Another common use of PLLs is recovery of digital data from serial data streams by locking a local clock signal onto the phase and frequency of the data transitions. The local clock signal is then used to clock a flip-flop or latch receiving input from the serial data stream.
FIG. 1
is a block diagram of a typical PLL
10
. PLL
10
comprises phase/frequency detector
12
, charge pump
14
, loop filter
16
, voltage-controlled oscillator (“VCO”)
18
and frequency divider
20
. PLL
10
receives a reference clock signal CLK
REF
having a frequency F
REF
and generates an output clock signal CLK
OUT
having a frequency F
OUT
that is aligned to the reference clock signal in phase. The output clock frequency is typically an integer (N) multiple of the reference clock frequency; with the parameter N set by frequency divider
20
. Hence, for each reference signal period, there are N output signal periods or cycles.
Phase/frequency signal detector
12
receives on its input terminals two clock signals CLK
REF
and CLK*
OUT
(CLK
OUT
, with its frequency F
OUT
divided down by frequency divider
20
). In a conventional arrangement, detector
12
is a rising edge detector that compares the rising edges of the two clock signals. Based on this comparison, detector
12
generates one of three states. If the phases of the two signals are aligned, the loop is “locked”. Neither the UP nor the DOWN signal is asserted and VCO
18
continues to oscillate at the same frequency. If CLK
REF
leads CLK*
OUT
, than VCO
18
is oscillating too slowly and detector
12
outputs an UP signal proportional to the phase difference between CLK
REF
and CLK*
OUT
. Conversely, if CLK
REF
lags CLK*
OUT
, than VCO
18
is oscillating too quickly and detector
12
outputs a DOWN signal proportional to the phase difference between CLK
REF
and CLK*
OUT
. The UP and DOWN signals typically take the form of pulses having a width or duration corresponding to the timing difference between the rising edges of the reference and output clock signals.
Charge pump
14
generates a current I
CP
that controls the oscillation frequency F
OUT
of VCO
18
. I
CP
is dependent on the signal output by phase/frequency detector
12
. If charge pump
14
receives an UP signal from detector
12
, indicating that CLK
REF
leads CLK*
OUT
, I
CP
is increased. If charge pump
14
receives a DOWN signal from detector
12
, indicating that CLK
REF
lags CLK*
OUT
, I
CP
is decreased. If neither an UP nor a DOWN signal is received, indicating that the clock signals are aligned, charge pump
14
does not adjust I
CP
.
Loop filter
16
is positioned between charge pump
14
and VCO
18
. Application of the charge pump output current I
CP
to loop filter
16
develops a voltage V
LF
across filter
16
. V
LF
is applied to VCO
18
to control the frequency F
OUT
of the output clock signal. Filter
16
also removes out-of-band, interfering signals before application of V
LF
to VCO
18
. A common configuration for a loop filter in a PLL is a simple single-pole, low-pass filter that can be realized with a single resistor and capacitor.
Oscillator
18
generates an oscillating output signal CLK
OUT
having a frequency F
OUT
proportional to the voltage V
LF
applied to VCO
18
. Conventional voltage-controlled oscillators typically oscillate about a specific center frequency and have a relatively narrow frequency range or bandwidth. When CLK
REF
leads CLK*
OUT
, charge pump
14
increases I
CP
to develop a greater V
LF
across loop filter
16
which, in turn, causes VCO
18
to increase F
OUT
. Conversely, when CLK
REF
lags CLK*
OUT
, charge pump
14
decreases I
CP
to develop a lesser V
LF
across loop filter
16
which, in turn, causes VCO
18
to decrease F
OUT
. When CLK
REF
and CLK*
OUT
are aligned, V
LF
is not adjusted, and F
OUT
is kept constant. In this state, PLL
10
is in a “locked” condition.
The output clock signal is also looped back through (in some applications) frequency divider
20
. The resultant output CLK*
OUT
is provided to phase/frequency detector
12
to facilitate the phase-locked loop operation. Frequency divider
20
facilitates comparison of the generally higher frequency output clock signal with the lower frequency reference clock signal by dividing F
OUT
by the multiplication factor N. Divider
20
may be implemented using counters, shift registers, or through other methods familiar to those of ordinary skill in the art. Thus, PLL
10
compares the reference clock phase to the output clock phase and eliminates any detected phase difference between the two by adjusting the frequency of the output clock.
As described above, phase-locked loops conventionally employ voltage-controlled oscillators to generate the output clock signal. Voltage-controlled oscillators, in turn, are often implemented in the form of ring oscillators. Ring oscillators are well known in the art and are typically comprised of an odd number of inverters connected in cascade, with the output of the last inverter in the series being connected to the input of the first inverter. Hence, the oscillator alternately generates logical ones and zeroes that propagate around the ring. Each inverter also acts as a delay element, wherein the delay of the inverter contributes to the oscillation period.
Ring oscillators are plagued by several drawbacks. Of chief concern, relative to the present invention, is the tendency of ring oscillators to accumulate a significant amount of jitter. Jitter is phase noise that is generated during PLL operation from a number of sources, including switching activity and substrate and supply noise. Each inverter generates a quantum of jitter that is transferred to successive stages. As the ring oscillator is essentially a continuous feedback loop, the jitter continuously propagates and accumulates. The jitter-per-cycle of a PLL employing a ring oscillator is expressed by the sum of the timing error contributed by each inverter weighted by the correction provided by the loop. The z-domain transfer function, &THgr;
out
(z), for the phase error of a PLL employing a ring oscillator may be represented as:
Θ
out
⁡
(
z
)
=
Θ
n
⁡
(
z
)
1
+
K
d
⁢
K
vco
⁢
Z
F
⁡
(
z
)
⁢
z
-
1
;
where K
d
is the gain of the phase detector, K
VCO
is the gain of the VCO, and Z
F
(z) is the z-domain transfer function of the loop filter. Assuming a first order loop filter transfer function is used, the z-domain transfer function for phase error becomes:
Θ
out
⁡
(
z
)
=
1
-
z
-
1
1
-
(
1
-
ϵ
)
⁢
z
-
1
⁢
Θ
n
⁡
(
z
)
;
where &egr;=K
d
K
VCO
aT and is smaller than one, wherein a is the DC gain of loop filter
16
and T is the period of the input reference signal
(
1
F
REF
)
,
and &THgr;

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