1984-11-14
1986-10-14
James, Andrew J.
357 36, H01L 2974
Patent
active
046175830
ABSTRACT:
A gate turn-off thyristor has a first emitter layer having a P.sup.+ P.sup.- emitter structure which is in contact with an anode electrode and a second emitter layer having an N-type multi-emitter structure which is in contact with cathode electrodes. To reduce power dissipation in the turn-off process, the first emitter layer mainly consists of low impurity concentration regions, and each high impurity concentration region is formed to have a substantially uniform width and to surround the low impurity concentration region formed within a region of the first emitter layer immediately below one of the emitter strips of the second emitter layer.
REFERENCES:
Patent Abstracts of Japan, vol. 8, No. 4, 10th Jan. 1984, p. (E-220) (1441).
International Power Electronics Conference, p. 65, T. Yatsuo et al, Mar. 27-31, 1983.
Asaka Masayuki
Shinohe Takashi
Crane Sara W.
James Andrew J.
Kabushiki Kaisha Toshiba
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