Gate transition counter

Details Gate transition counter Gate transition counter

2000-08-11

2002-05-28

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synthesizer

C331S045000, C331S057000

Reexamination Certificate

active

06396312

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the field of timing circuits. More particularly, this invention relates to an apparatus and method for use of a ring counter to count gate transitions.
BACKGROUND OF THE INVENTION
In many circuit applications, it is common to measure time in discrete time segments that might be unrelated to conventional time measurements (e.g. seconds or microseconds). A simple example is the number of clock transitions that a microprocessor requires to complete a given task (for example, an add or divide operation). In another example, if a circuit operates using a conventional clock circuit having a clock period of T, it might be necessary to establish a logic transition to occur at approximately {fraction (1/16)} of the time period T after the clock transition. Latches and/or registers configured as a counter might be conventionally used to establish such transition times by accumulating the time delay associated with several latches or registers to produce the desired time delay. Since such latches and registers have delays caused by multiple gate transitions, they can have relatively long delays associated with them. In many applications, particularly at higher frequencies, the time delay associated with toggling a latch or register is not a small enough time increment to provide adequate resolution to achieve a desired timing accuracy. Consider a 1.8 micron CMOS circuit example wherein a clock period T is 2.0 nanoseconds, a gate delay is 30 picoseconds and a latch requires six gate delays or 180 picoseconds. In this example, T/16=125 picoseconds. Thus, in this example, one latch delay is far too large to approximate the required {fraction (1/16)} of a clock period for most applications. In general, for this application, the desired time can only be guaranteed within about three gate delays (half of the six gate delays of the latch).
Moreover, integrated circuit processing variations can change the absolute time associated with a given latch and register by significant amounts. This compounds the problem of using a latch or register in some circumstances, since the error in resolution can be exaggerated by processing variations. Considering the above example, if the clock period is fixed (e.g. by a crystal controlled oscillator), a processing variation resulting in only a 10% increase in gate delay time would result in a latch delay of 198 picoseconds—even further from the required T/16=125 picoseconds.
Therefore, it would be advantageous to use the smallest time measurement increment available to minimize such errors. In the case of integrated circuit design, the smallest delay time is generally a single gate transition. However, due to significant variations in processing parameters, the absolute number of gate transitions also cannot be reliably known. In the above example, four gate transitions equals 120 picoseconds, which approximates the required 125 picoseconds good enough for many applications. However, those skilled in the art will appreciate that one gate transition time for this process might range from about 20 picoseconds to 50 picoseconds. This means that the exact number of gate transitions required to approximate 125 picoseconds could be anywhere from two to six gate transitions.
BRIEF SUMMARY OF THE INVENTION
The present invention relates generally to a gate transition counter circuit and methods therefor. Objects, advantages and features of the invention will become apparent to those skilled in the art upon consideration of the following detailed description of the invention.
In one embodiment of the present invention, a circuit consistent with the present invention that counts gate transitions includes a ring oscillator having a plurality of N inverting circuits, where N is an odd integer, each inverting circuit having an input and an output. The inverting circuits are connected together, input to output, to form a continuous loop. The circuit includes an input for receiving a halt control signal to halt the oscillation of the ring oscillator. The circuit also includes a plurality of N latches, each latch having an input and an output, with each of the N latch inputs connected to one of the N inverter circuit outputs. The halt control signal is coupled to the plurality of N latches to capture the output of the N inverting circuits when the halt control signal is received.
In another embodiment, a circuit consistent with the present invention that counts gate transitions includes a ring oscillator having a plurality of N inverting circuits, where N is an odd integer. Each inverting circuit has an input and an output. The inverting circuits are connected together input to output to form a continuous loop. The ring oscillator includes a circuit for receiving a start control signal to start the oscillation of the ring oscillator and a circuit for receiving a halt control signal to halt the oscillation of the ring oscillator. A plurality of N buffers is provided, and a plurality of N latches, each having an input and an output, has each of the N latch inputs connected to one of the N inverter circuit outputs through one of the N buffers. The halt control signal is coupled to the plurality of N latches to capture the output of the N inverting circuits when the halt control signal is received. A ripple counter has an input coupled to one of the latch outputs. The ripple counter counts a number of transitions of the latch output and produces a ripple counter output. A logic circuit receives the N latch outputs and converts the N latch outputs to a binary value.
A method, consistent with certain embodiments of the present invention, of capturing the state of a ring oscillator, wherein the ring oscillator includes a plurality of N inverting circuits, where N is an odd integer, each inverting circuit having an input and an output, the inverting circuits being connected together input to output to form a continuous loop, includes: causing the ring oscillator to oscillate; receiving a halt control signal to halt the oscillation of the ring oscillator; and latching a value at each output in one of a plurality of N latches to create a latched value R.
In another method consistent with the present invention, of capturing the state of a ring oscillator, the ring oscillator comprising a plurality of N logic gates, each gate having an input and an output, the gates being connected together input to output to form a continuous loop, the method includes: causing the ring oscillator to oscillate; receiving a halt control signal to halt the oscillation of the ring oscillator; and latching a value at each output in one of a plurality of N latches to create a latched value R.
Many variations, equivalents and permutations of the above illustrative exemplary embodiments of the invention will occur to those skilled in the art upon consideration of the description that follows. The particular examples above should not be considered to define the scope of the invention.


REFERENCES:
patent: 5126691 (1992-06-01), Mijuskovie et al.
patent: 5528200 (1996-06-01), Yamauchi et al.
patent: 5534809 (1996-07-01), Watanabe et al.
patent: 5684760 (1997-11-01), Hunter

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