Gate structure forming method of field effect transistor

Details Gate structure forming method of field effect transistor Gate structure forming method of field effect transistor

2003-08-06

2004-08-31

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Forming schottky junction

Compound semiconductor

C438S577000, C438S579000, C438S951000

Reexamination Certificate

active

06784081

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for a gate structure of field effect transistor (FET).
2. Description of Related Art
The metal semiconductor field effect transistor (MESFET) or the high electron mobility transistor (HEMT) is a microwave device. In order to increase the operation frequency and efficiency, reducing the gate length and suppressing the signal noise are feasible approaches. However, as devices enter the sub-micron stage, the resistance of the gate increases as the gate length reduces. In order to overcome the aforementioned problem, a T-shaped gate structure technique is widely used. Further, simpler manufacturing techniques are also being developed.
FIGS. 1A
to
1
D are schematic, cross-sectional diagrams illustrating a process flow for fabricating a T-shaped gate structure according to the prior art.
Referring to
FIG. 1A
, a photoresist layer
102
and a photoresist layer
104
are formed on a substrate
100
. An electron beam exposure process
106
is then conducted on the photoresist layer
102
and the photoresist layer
104
, wherein the energy of the main beam
106
a
is greater than the energy of the side beam
106
b.
Referring to
FIG. 1B
, a two-step development process is conducted to form the patterned photoresist layer
102
a
and the patterned photoresist layer
104
a
, wherein at the region where the electron beam
106
a
(higher energy) is directed to, both photoresist layers
102
a
,
104
a
are being developed, whereas at the region where the electron beam
106
b
(lower energy) is directed to, only the photoresist layer
104
a
is being developed.
Referring to
FIG. 1C
, a metal evaporation deposition process is conducted to form a metal layer
108
on the exposed surface of the substrate
100
and on the photoresist layers
102
a
,
104
a
, wherein the metal layer
108
a
that is formed on the substrate
100
surface and the photoresist layer
102
a
is separated from the metal layer that is formed on the photoresist layer
104
a.
Continuing to
FIG. 1D
, the photoresist layers
102
a
,
104
a
are removed. Concurrently, the metal layer
108
b
is also being striped, leaving only the metal layer
108
a
to form a T-shaped gate structure.
However, in the aforementioned method, the fabrication of the gate structure requires the application of the electron beam development process. The manufacturing cost is thus higher and a lower throughput is resulted (1 to 2 wafer per hour). Further, seam may be generated on the surface of the subsequently formed metal layer (gate structure) when the rounding of the lower photoresist layer profile is not sufficient. The reliability of the device is thus affected.
FIGS. 2A
to
2
D are schematic, cross-sectional diagrams illustrating a process flow for fabricating another type of gate structure.
As shown in
FIG. 2A
, a patterned silicon nitride layer
202
is formed on a substrate
200
, exposing a part of the substrate
200
. A photoresist layer
204
is then formed over the silicon nitride layer
204
.
Referring to
FIG. 2B
, a photolithography process is conducted to pattern the photoresist layer
204
to form the photoresist layer
204
a
. The photoresist layer
204
a
exposes a part of the silicon nitride layer
202
and a substrate
200
surface exposed by the silicon nitride layer
202
.
Continuing to
FIG. 2C
, a metal evaporation deposition process is conducted to form a metal layer
206
on the photoresist layer
204
a
, the exposed silicon nitride layer
202
and the substrate
200
surface, wherein the metal layer
206
b
formed on the photoresist layer
204
a
is separated from the metal layer
206
a
on the silicon nitride layer and the substrate
200
surface.
Referring to
FIG. 2D
, the photoresist layer
204
a
is removed. Concurrently, the metal layer
206
b
is striped, leaving only the metal layer
206
a
to serve as a T-shaped gate structure.
However, when a gate structure is formed with the above methods, parasitic capacitance is formed between the gate, the silicon nitride layer and the substrate due to a direct contact between the top surface of the silicon nitride layer and the substrate. The presence of a parasitic capacitance lowers the cutoff frequency and the maximum transition frequency. As a result, noise interference increases during the operation of the device.
SUMMARY OF INVENTION
Accordingly, the present invention provides a fabrication method for a gate structure, wherein the deficiencies in the conventional manufacturing method for a T-shaped gate structure, for example, high cost and low yield, are resolved.
The present invention also provides a fabrication method for a gate structure, wherein the generation of parasitic capacitance at the gate formed according the conventional manufacturing method for a T-shaped gate structure is resolved.
The present invention further provides a fabrication method for a metal semiconductor field effect transistor, wherein the reliability of a device is improved and a better operation efficiency is resulted.
The present invention provides a fabrication method for a gate structure, wherein a pad layer is formed on a surface of a substrate. A patterned first photoresist layer is formed on the pad layer, wherein the patterned first photoresist layer exposes the pad layer. An ultra-violet curing step is conducted to form a cross-linked layer at the surface of the first photoresist layer. Thereafter, a rounding step is conducted for rounding the profile of the first photoresist layer. The pad layer that is not covered by the first photoresist layer is then removed to expose a surface of the substrate. A patterned second photoresist layer is then formed on the first photoresist layer, wherein the second photoresist layer exposes a part of the first photoresist layer and the substrate surface that is being exposed by the first photoresist layer. A deposition step is conducted to form a conductive layer on the second photoresist layer, the first photoresist layer and the surface of the substrate, wherein the conductive layer formed on the second photoresist layer is separated from the metal layer formed on the first photoresist layer and the substrate surface. The first photoresist layer and the second photoresist layer are then removed, wherein the conductive layer formed on the second photoresist layer is concurrently striped, and the remaining conductive layer serves as a gate.
Thereafter, the pad layer is then patterned. Subsequent to the formation of a source/drain region on the surface of the substrate, a metal semiconductor field effect transistor is formed.
Since the T-shaped gate structure formed according to the present invention is not in a direct contact with the top surface of the pad layer, the generation of parasitic capacitance as in the conventional technique is thus prevented.
Further, in the fabrication method for a gate structure of the present invention, expensive and low yield manufacturing apparatus are precluded. The present invention thus provides a low cost and high yield manufacturing method for a gate structure.
Further, the gate electrode of the metal semiconductor field effect transistor of the present invention is a T-shaped gate electrode, which has a low resistance and no parasitic capacitance. The reliability and the operation efficiency of the device of the present invention are thereby desirable.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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