1987-03-16
1990-05-08
Wojciechowicz, Edward J.
357 231, 357 59, 357 67, 357 71, H01L 2978
Patent
active
049242814
ABSTRACT:
A gate structure of a MOS FET has an oxide layer and an electrode layer sequentially formed on a silicon substrate. In the gate structure, the electrode layer includes a first silicidized high-melting metal layer formed on the oxide layer, a high-melting metal layer formed on the first silicidized high-melting metal layer and a second silicidized high-melting metal layer formed on the high-melting metal layer.
REFERENCES:
patent: 4263058 (1981-04-01), Brown et al.
patent: 4337476 (1982-06-01), Fraser
patent: 4485550 (1984-12-01), Koeneke et al.
patent: 4581627 (1986-04-01), Ueda et al.
Murarka et al.--IEEE Jour. Solid-State Circuits, vol. SC-15, No. 4, Aug. 1980, "Refractory Silicides of titanium and Tantalum for Low-Resistivity Gates and Intercorrects".
Endo Kazuo
Mitani Tatsuro
Noda Noboru
Kabushiki Kaisha Toshiba
Wojciechowicz Edward J.
LandOfFree
Gate structure for a MOS FET does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Gate structure for a MOS FET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate structure for a MOS FET will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2352756