Gate stack and etch process

Details Gate stack and etch process Gate stack and etch process

1998-01-28

2003-08-19

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S710000, C438S712000

Reexamination Certificate

active

06607985

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit gate structures which contain unreacted metal, and to methods for fabricating such structures.
One of the driving forces in shrinking integrated circuit geometries is the distributed resistance and parasitic capacitance of the signal lines, which reduce the propagation speed of signals. The additional delays thus introduced reduce the potential speed of the chip.
This is a particular problem for DRAMs, since the wordlines are densely packed together, and the capacitive coupling between adjacent lines becomes very significant. Moreover, the sheet resistance of the lines cannot usefully be improved by increasing the height of the lines, since this also increases the capacitive coupling between adjacent lines. There has therefore been great pressure to find materials with a lower resistivity to replace the traditional polysilicon/silicide lines. This has impelled efforts to design metal into the gate line structure. One example of this is a gate stack structure which includes tungsten over a metal nitride over polysilicon, but many other gate stack structures have been proposed.
A further difficulty with gate stack etching is that some topography is present, since with conventional isolation technologies the gate stack will be higher atop field oxides than on the active (moat) areas. Thus a substantial amount of overetch is required to fully clear the gate stack from the areas to be etched.
However, complicated DRAM transistor gate stacks have proved difficult to etch. Previous etches have lower inter-layer selectivities and lower etch uniformity. These etches will only work on stacks with a thick polysilicon layer and minimal wafer topography where it is possible to stop in the polysilicon layer before exposing and removing the gate oxide and then switching to the polysilicon etch step. Previous etches also do not have the profile control required to etch gates with lengths of 0.25 microns and below.
Stack Etch Process
The proposed etch process overcomes the above difficulties by utilizing an integrated set of low pressure, high-density-plasma process conditions with high inter-layer selectivity. The proposed highly selective and uniform etch process can stop in a thin (sub-100 nm) polysilicon layer even with LOCOS topography which requires a 100 percent over-etch of each layer in the DRAM stack to clear stringers at the moat boundary.
The advantages of the proposed etch process include:
excellent etch rate uniformity across the wafer (<3 percent typical non-uniformity);
high etch selectivity between the gate stack layers (silicon nitride:tungsten 2.4:1, tungsten:titanium nitride 5.5:1, polysilicon:oxide 420:1);
possible to perform long over-etches (100 percent) of the in dividual layers which is required with severe wafer topography;
gate profiles are nearly 90 degrees on 0.25 micron gates; minimal gate oxide loss (<2 nanometers typically); gate lengths are very uniform across the wafer surface; and high throughput process if performed on a cluster platform.


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