Gate/source disturb protection for sixteen-bit flash EEPROM memo

Details Gate/source disturb protection for sixteen-bit flash EEPROM memo Gate/source disturb protection for sixteen-bit flash EEPROM memo

1992-06-19

1994-05-31

LaRoche, Eugene R.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 36523003, 3652385, 365900, G11C 1134, G11C 700, G11C 800

Patent

active

053175352

ABSTRACT:
In a flash EEPROM memory array in which a plurality of floating gate field effect transistor memory devices are arranged in rows and columns, in which wordlines are utilized to select rows of such devices and bitlines are utilized to select columns of such devices, in which groups of such devices are arranged in blocks which are independently erasable, and the blocks are divided into sub-blocks for storing lower and upper bytes of words to be stored, apparatus is provided for disabling the wordlines to all high byte sub-blocks when a low byte sub-block is to be programmed, for disabling the wordlines to all low byte sub-blocks when a high byte sub-block is to be programmed, for grounding the sources of all high byte sub-blocks when a low byte sub-block is to be programmed, and for grounding the sources of all low byte sub-blocks when a high byte sub-block is to be programmed.

REFERENCES:
patent: 4775958 (1988-10-01), Hashimoto
patent: 5033024 (1991-07-01), O'Connell et al.
patent: 5034926 (1991-07-01), Taura et al.
patent: 5065364 (1991-11-01), Atwood et al.
patent: 5095461 (1992-03-01), Miyakawa et al.

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