Gate processor arrangement for simulation processor system

Details Gate processor arrangement for simulation processor system Gate processor arrangement for simulation processor system

1988-02-19

1990-07-17

Gruber, Felix D.

Boots, shoes, and leggings

364200, 3642323, G06F 944, G01R 3128

Patent

active

049426150

ABSTRACT:
A gate processor arrangement for a logic simulation processor system includes a new event buffer memory for storing an event at a timing t.sub.a for a predetermined logic element in a section of a logic network. A fan-out device for holding connection information for the predetermined logic element in the section of the logic network and reading the data of the predetermined logic element precedingly at a timing t is also provided. The input data of the predetermined logic element is changed at a timing "t+1". An evaluation gate buffer memory is provided having a plurality of evaluation gate memory portions able to be connected to the fan-out device and an evaluation device. The arrangement also includes a net status memory for holding net status information corresponding to input data and output data of a predetermined logic element in the section of the logic network; and an evaluation device responsive to the output of the evaluation gate buffer memory for reading the data in the net status memory, generating information for the change of the network status at a timing "t+1", and supplying the generated information to the event transmission network and/or the new event buffer memory.

REFERENCES:
patent: 4527249 (1985-07-01), Van Brunt
patent: 4669083 (1987-05-01), Laviron
patent: 4769817 (1988-09-01), Krohn et al.
patent: 4775950 (1988-10-01), Terada et al.
patent: 4782440 (1988-11-01), Nomizu et al.
patent: 4787061 (1988-11-01), Nei et al.

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