Gate process for NMOS ESD protection circuits

Details Gate process for NMOS ESD protection circuits Gate process for NMOS ESD protection circuits

1995-04-27

1996-07-02

Thomas, Tom

Fishing, trapping, and vermin destroying

437 34, 437 44, 437 41, 257360, H01L 2170

Patent

active

055321780

ABSTRACT:
An improved process and integrated-circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate and a NMOS electro static discharge circuit formed in a P well on the substrate. The improvement includes an electro static discharge NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes. The undoped polysilicon gate electrode of the electro static discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.

REFERENCES:
patent: 4692834 (1987-09-01), Iwahashi et al.
patent: 5208475 (1993-05-01), Mortensen
patent: 5262344 (1993-11-01), Mistry
patent: 5301084 (1994-04-01), Miller

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