Patent
1989-01-17
1990-05-22
Hille, Rolf
357 51, 357 45, H01L 2934, H01L 2702, H01L 2710
Patent
active
049281607
ABSTRACT:
A CMOS gate isolated gate array configured with a single polysilicon layer and preferably two metallization layers, wherein the cell pitch is equal to the first and second metallization pitches by referencing the metallization layers, contacts and vias to a grid, and referencing the polysilicon layer to a half grid. Further refinements include the use of channel regions between parallel and adjacent chains of complementary transistors, wherein the width of the channel is equal to three times the pitch of the cell. In another form, a base set of the gate array includes diffused resistors in the channel regions suitable for matching discretionary interconnection.
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Enest L. Meyer, "Garnering the Gates in High-Density Arrays", 1988 Semicustom Design Guide.
"VLSI to Take Designs on Array Line", Electronic News, Mar. 21, 1988, p. 27.
Fahmy Wael
Hawk Jr. Wilbert
Hille Rolf
NCR Corporation
Salys Casimer K.
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