Gate insulation layer and method of producing such a structure

Metal working – Method of mechanical manufacture – Assembling or joining

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

29576R, 29589, 357 54, 357 235, 427 92, 4271264, 427437, 365182, 148DIG118, H01L 2978

Patent

active

045661731

ABSTRACT:
The method in accordance with the invention is used for the production of field-effect transistors and preferably implemented in such a manner that a thin aluminum layer (2) is deposited on the surface of a silicon substrate (1), for example, by means of a basic cleaning solution containing aluminum, that subsequently thermal oxidation is effected, during which, in addition to a silicon dioxide layer (3), an about 1 to 1.5 nm thick layer (4) containing aluminum oxide and silicon dioxide is formed and that finally, if required, at least one further layer, for example, an Si.sub.3 N.sub.4 (5) or an Si.sub.3 N.sub.4 (5) and an SiO.sub.2 layer are deposited. By adding about 400 ppb aluminum to the cleaning solution, which in the finished structure equals a quantity of aluminum of about 250 pg/cm.sup.2 layer surface, the threshold voltage V.sub.S is raised by about 470 millivolts.
The structure produced in accordance with the invention is used in particular in N-channel field-effect transistors of the enrichment type which in series connection are integrated in great number and at high density on semiconductor substrates.

REFERENCES:
patent: 2722491 (1955-11-01), Anderson
patent: 2890971 (1959-06-01), Arnold et al.
patent: 3228795 (1966-01-01), Ackermann
patent: 3665265 (1972-05-01), Fujimoto
patent: 3668004 (1972-06-01), Yamamoto et al.
patent: 3974003 (1976-08-01), Zirinsky et al.
patent: 3978577 (1976-09-01), Bhattacharyya et al.
patent: 4025669 (1977-05-01), Greenstein
patent: 4115914 (1978-09-01), Harari
patent: 4151537 (1979-04-01), Goldman et al.
patent: 4151538 (1979-04-01), Polinsky et al.
patent: 4244986 (1981-01-01), Paruso et al.
patent: 4416911 (1983-11-01), Wilkinson-Tough
Jacobs et al.; "N-Channel Si Gate Process for MNOS EEPROM Transistors", Solid State Elec., vol. 24, pp. 517-522, 1981.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Gate insulation layer and method of producing such a structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Gate insulation layer and method of producing such a structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Gate insulation layer and method of producing such a structure will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1298988

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.