Gate insulation layer and method of producing such a structure

Details Gate insulation layer and method of producing such a structure Gate insulation layer and method of producing such a structure

1982-06-04

1986-01-28

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576R, 29589, 357 54, 357 235, 427 92, 4271264, 427437, 365182, 148DIG118, H01L 2978

Patent

active

045661731

ABSTRACT:
The method in accordance with the invention is used for the production of field-effect transistors and preferably implemented in such a manner that a thin aluminum layer (2) is deposited on the surface of a silicon substrate (1), for example, by means of a basic cleaning solution containing aluminum, that subsequently thermal oxidation is effected, during which, in addition to a silicon dioxide layer (3), an about 1 to 1.5 nm thick layer (4) containing aluminum oxide and silicon dioxide is formed and that finally, if required, at least one further layer, for example, an Si.sub.3 N.sub.4 (5) or an Si.sub.3 N.sub.4 (5) and an SiO.sub.2 layer are deposited. By adding about 400 ppb aluminum to the cleaning solution, which in the finished structure equals a quantity of aluminum of about 250 pg/cm.sup.2 layer surface, the threshold voltage V.sub.S is raised by about 470 millivolts.
The structure produced in accordance with the invention is used in particular in N-channel field-effect transistors of the enrichment type which in series connection are integrated in great number and at high density on semiconductor substrates.

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Jacobs et al.; "N-Channel Si Gate Process for MNOS EEPROM Transistors", Solid State Elec., vol. 24, pp. 517-522, 1981.

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