Gate injected floating gate memory device

Details Gate injected floating gate memory device Gate injected floating gate memory device

1979-10-19

1981-02-24

Edlow, Martin H.

357 54, H01L 2978

Patent

active

042531063

ABSTRACT:
An improved gate injected, floating gate memory device is described having improved charge retention and endurance characteristics is described in which the barrier height for the injection of charge (electrons or holes) into the floating gate is reduced. This is accomplished by utilizing a layer of semi-insulating polycrystalline silicon between the control electrode and the insulating layer over the floating gate.

REFERENCES:
patent: 3649884 (1972-03-01), Haneta
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patent: 3868187 (1975-02-01), Masuoka
patent: 4057820 (1977-11-01), Gallagher
patent: 4104675 (1978-08-01), DiMaria
patent: 4115914 (1978-09-01), Harari
patent: 4119995 (1978-10-01), Simko
patent: 4162504 (1979-07-01), Hsu
Mochizuki et al., Proceed 7th Conf. Solid State Devices, Tokyo, 1975, pp. 41-48.
Matsushita et al., Proceed 7th Conf. Solid State Devices, Toyko, 1975, pp. 35-40.
DiMaria, Jour. of Appli. Phys. vol. 50, No. 9, Sep. 1979, pp. 5826-5829.

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