Gate having temperature-stabilized delay

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307254, 307491, 323313, H03K 5159, G06G 710

Patent

active

046510389

ABSTRACT:
A circuit technique for stabilizing the timing of signals at an output node of a gate, despite substantial variations in temperature. In a gate having a switching portion and an emitter follower, the temperature-dependence of the gate delay within the switching portion may be offset by suitable control of the temperature characteristics of the load current source supplying the emitter follower output node. The load current source comprises a current source resistor, a current source transistor having its collector coupled to the output node, and a reference voltage source. The voltage source, rather than having a zero temperature coefficient as in known temperature-compensated configurations, is configured to have a temperature coefficient chosen to provide a temperature dependence in the delay through the emitter follower that offsets the temperature dependence of the delay through the switching portion so that the total gate delay is substantially temperature-independent. The reference voltage source for the load current source is a modified band-gap regulator comprising a regulating transistor, a current source pair of transistors Q1 and Q2, and first, second, and third resistors. The third resistor changes the current relationships to provide the desired output voltage and temperature coefficient.

REFERENCES:
patent: 4249091 (1981-02-01), Yamagiwa
patent: 4323854 (1982-04-01), Hester
patent: 4424461 (1984-01-01), Taguchi et al.
patent: 4532441 (1985-07-01), Gloaguen

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